QF1DA512-DK Quickfilter Technologies LLC, QF1DA512-DK Datasheet - Page 22

• Manufacturer Part Number: QF1DA512-DK
• Description: KIT DEV FOR QF1DA512
• Manufacturer: Quickfilter Technologies LLC
• Series: SavFIRe™r

Specifications of QF1DA512-DK

• Main Purpose: Filters, Digital Filter Design
• Embedded: Yes, ASIC
• Utilized Ic / Part: QF1Da512
• Primary Attributes: 1 512 Tap FIR Filter, 12 ~ 24 Bit
• Secondary Attributes: Quickfilter Software Design Tool GUI, Works from 10 ~ 500ksps ADC Data Rates
• For Use With: WM2582 - EVALDI EARBUDS TYPE Y686-1006 - BOARD MSP-MOJO + EXPANSION HEADR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 686-1010

→ 5
Rev A8 January 7, 2009
04h DCONFIG (Data Format Control)
POR
Bits
DUP
MODE1
MODE0
FORMAT
dCS_POL1-
dCS_POL0
dSCK_POL
cSCK_POL
–
Duplicates (but does not alter) dSDI on channel selected by dCS_POL to output dSDO. Requires
DECIMATE (08h) =00h and dCS as per above.
0 = Input data is not duplicated.
1 = Input data is duplicated.
Selects the data input mode.
00 = Input data mode is SPI Normal Mode.
01 = Input data mode is SPI Continuous Mode.
10 = Input data mode is Synchronous serial mode
10 = Input data mode is I2S Mode
Selects the data format of the incoming data.
0 = Incoming data format is 2‟s complement.
1 = Incoming data format is offset binary.
Selects polarity of the dCS pin for SPI and Synchronous serial modes. Also used in processing I2S
00 = dCS is active low for SPI modes and Synchronous serial mode when only a single edge/level is
being used as a trigger
01 = dCS is active high for SPI modes and Synchronous serial mode when only a single edge/level is
being used as a trigger
1X = dCS is active both high and low. This is the normal mode for I2S data.
If DUP = 1 (Duplication Mode for I2S formatted data)
10 = Filter the incoming left channel data (the data where dCS is low) and place the filtered data on
11 = Filter the incoming right channel data (the data where dCS is low) and place the filtered data on
Selects the clock edge of dSCK on which the data on the dSDI pin is captured. dSDO is output on
the opposite edge (Filter mode).
0 = dSDI is captured on the falling edge of dSCK.
1 = dSDI is captured on the rising edge of dSCK.
The clock edge of cSCK on which the data on the cSDI is captured. cSDO is output on the opposite
edge.
0 = cSDI data is captured on the falling edge of cSCK.
1 = cSDI data is captured on the rising edge of cSCK.
DUP
Bit 7
RW
0
data if the DUP bit is set.
the dSDO left channel output. Copy (unaltered) the incoming left channel data to the right
channel on dSDO.
the dSDO right channel output. Copy (unaltered) the incoming right channel data to the left
channel on dSDO.
MODE1
Bit 6
RW
1
PRELIMINARY DATA SHEET
MODE0
Bit 5
RW
0
22
FORMAT
Bit 4
RW
0
dCS_POL1
Bit 3
RW
1
dCS_POL0
Bit 2
RW
0
dSCK_POL
Bit 1
RW
1
www.quickfiltertech.com
cSCK_POL
Bit 0
RW
1
QF1Da512