AFBR-5103ATZ Avago Technologies US Inc., AFBR-5103ATZ Datasheet - Page 8

• Manufacturer Part Number: AFBR-5103ATZ
• Description: TXRX OPT 1X9 100MBPS DUPL ST SIP
• Manufacturer: Avago Technologies US Inc.

Specifications of AFBR-5103ATZ

• Data Rate: 100Mbps
• Wavelength: 1300nm
• Applications: General Purpose
• Voltage - Supply: 4.75 V ~ 5.25 V
• Connector Type: ST
• Mounting Type: Through Hole
• Function: Implement FDDI and ATM at the 100 Mbps/125 MBd rate
• Product: Transceiver
• Maximum Rise Time: 3 ns, 2.2 ns
• Maximum Fall Time: 3 ns, 2.2 ns
• Pulse Width Distortion: 0.02 ns
• Maximum Output Current: 50 mA
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: SIP-9
• For Use With: Multimode Glass
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 516-1981

Solder and Wash Process Compatibility
The trans­ceivers­ are delivered with protective proces­s­
plugs­ ins­erted into the duplex SC or duplex ST connector
receptacle.
This­ proces­s­ plug protects­ the optical s­ubas­s­emblies­ dur-
ing wave s­older and aqueous­ was­h proces­s­ing and acts­ as­
a dus­t cover during s­hipping.
Thes­e trans­ceivers­ are compatible with either indus­try
s­tandard wave or hand s­older proces­s­es­.
Shipping Container
The trans­ceiver is­ packaged in a s­hipping container de-
s­igned to protect it from mechanical and ESD damage
during s­hipment or s­torage.

Figure 7. Recommended Decoupling and Termination Circuits
TERMINATION
AT PHY
DEVICE
INPUTS
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS NEED TO BE LOCATED AT THE INPUT
OF DEVICES RECEIVING THOSE ECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT
BOARD WITH 50 OHM MICROSTRIP SIGNAL PATHS BE USED.
R1 = R4 = R6 = R8 = R10 = 130 OHMS.
R2 = R3 = R5 = R7 = R9 = 82 OHMS.
C1 = C2 = C3 = C5 = C6 = 0.1 µF.
C4 = 10 µF.
L1 = L2 = 1 µH COIL OR FERRITE INDUCTOR.
NO INTERNAL CONNECTION
V
Rx
R6
EE
1
RD
R5
RD
2
V
CC
C6
Rx
R7
RD
RD
3
R8
SD
SD
4
AFBR-510XZ
R10
TOP VIEW
R9
C1
V
C3
TRANSCEIVER
Rx
AT V
CC
5
V
CC
L1
V
CC
FILTER
CC
PINS
V
Tx
C4
CC
6
L2
NO INTERNAL CONNECTION
TD
C2
Tx
7
TD
TERMINATION
AT TRANSCEIVER
INPUTS
R1
TD
R2
8
V
CC
V
C5
Tx
R3
EE
9
R4
TD
Board Layout - Decoupling Circuit and Ground
Planes
It is­ important to take care in the layout of your circuit board
to achieve optimum performance from thes­e trans­ceivers­.
Figure 7 provides­ a good example of a s­chematic for a
power s­upply decoupling circuit that works­ well with thes­e
parts­. It is­ further recommended that a contiguous­ ground
plane be provided in the circuit board directly under the
trans­ceiver to provide a low inductance ground for s­ignal
return current. This­ recommendation is­ in keeping with
good high frequency board layout practices­.
Board Layout - Hole Pattern
The Avago Technologies­ trans­ceiver complies­ with the
circuit board “Common Trans­ceiver Footprint” hole pattern
defined in the original multis­ource announcement which
defined the 1x9 package s­tyle. This­ drawing is­ reproduced
in Figure 8 with the addition of ANSI Y14.5M compliant
dimens­ioning to be us­ed as­ a guide in the mechanical
layout of your circuit board.
Board Layout - Mechanical
For applications­ providing a choice of either a duplex SC or
a duplex ST connector interface, while utilizing the s­ame
pinout on the printed circuit board, the ST port needs­ to
protrude from the chas­s­is­ panel a minimum of 9.53 mm
for s­ufficient clearance to ins­tall the ST connector.
Pleas­e refer to Figure 8A for a mechanical layout detailing
the recommended location of the duplex SC and duplex ST
trans­ceiver packages­ in relation to the chas­s­is­ panel.
For both s­hielded des­ign options­, Figure 8b identifies­ front
panel aperture dimens­ions­.