MT9HVF6472PY-80ED1 Micron Technology Inc, MT9HVF6472PY-80ED1 Datasheet - Page 16

• Manufacturer Part Number: MT9HVF6472PY-80ED1
• Description: MODULE DDR2 512MB 240-DIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF6472PY-80ED1

• Memory Type: DDR2 SDRAM
• Memory Size: 512MB
• Speed: 800MT/s
• Package / Case: 240-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 13: DDR2 I
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
PDF: 09005aef81de9391
hvf9c32_64_128x72py.pdf - Rev. E 03/10 EN
Parameter
Operating one bank active-precharge current:
t
tween valid commands; Address bus inputs are switching; Data bus
inputs are switching
Operating one bank active-read-precharge current: I
BL = 4, CL = CL (I
t
valid commands; Address bus inputs are switching; Data pattern is
same as I
Precharge power-down current: All device banks idle;
(I
Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
(I
are stable; Data bus inputs are floating
Precharge standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are
switching; Data bus inputs are switching
Active power-down current: All device banks
open;
address bus inputs are stable; Data bus inputs are
floating
Active standby current: All device banks open;
t
tween valid commands; Other control and address bus inputs are
switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
MAX (I
mands; Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous
burst read, I
t
tween valid commands; Address bus inputs are switching; Data bus
inputs are switching
Burst refresh current:
t
Other control and address bus inputs are switching; Data bus inputs
are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control
and address bus inputs are floating; Data bus inputs are floating
RC =
RAS MIN (I
RAS =
RAS =
RFC (I
DD
DD
); CKE is LOW; Other control and address bus inputs are stable;
); CKE is HIGH, S# is HIGH; Other control and address bus inputs
t
DD
RC (I
t
DD
CK =
t
t
RAS MAX (I
RAS MAX (I
) interval; CKE is HIGH, S# is HIGH between valid commands;
DD4W
),
DD
DD
t
RP =
OUT
t
CK (I
),
),
t
t
RAS =
= 0mA; BL = 4, CL = CL (I
RCD =
DD
t
DD
RP (I
), AL = 0;
DD
DD
DD
); CKE is LOW; Other control and
),
),
DD
t
t
RAS MIN (I
Specifications and Conditions (Die Revision E) – 1GB
RCD (I
t
t
RP =
RP =
t
); CKE is HIGH, S# is HIGH between valid com-
CK =
t
CK =
t
t
DD
DD
RP (I
RP (I
t
CK (I
); CKE is HIGH, S# is HIGH between
), AL = 0;
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM
DD
t
DD
DD
CK (I
DD
); CKE is HIGH, S# is HIGH be-
); CKE is HIGH, S# is HIGH be-
); CKE is HIGH, S# is HIGH be-
); REFRESH command at every
DD
DD
t
),
CK =
), AL = 0;
t
RC =
t
CK (I
t
t
RC (I
CK =
t
CK =
t
t
DD
CK =
CK =
DD
),
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
CK (I
t
t
),
RAS =
CK (I
t
t
OUT
CK =
t
CK (I
t
t
CK (I
RAS =
CK =
16
DD
= 0mA;
DD
DD
),
t
DD
t
CK
RAS
),
t
CK
),
);
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Symbol
I
I
I
I
I
I
I
DD4W
DD2Q
I
I
DD2N
DD3N
DD4R
I
I
DD2P
DD3P
DD0
DD1
DD5
DD6
-80E/
-800
1665
1710
2520
900
990
585
630
405
126
675
63
63
1440
1440
2340
-667
810
900
495
540
360
126
630
63
63
© 2006 Micron Technology, Inc. All rights reserved.
I
DD
1170
1305
2250
-53E
720
855
369
405
315
126
495
63
63
Specifications
-40E
1980
630
720
315
360
315
126
405
990
990
63
63
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA