MT4VDDT1664HY-335F3 Micron Technology Inc, MT4VDDT1664HY-335F3 Datasheet - Page 20
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MT4VDDT1664HY-335F3
Manufacturer Part Number
MT4VDDT1664HY-335F3
Description
MODULE DDR 128MB 200-SODIMM
Manufacturer
Micron Technology Inc
Specifications of MT4VDDT1664HY-335F3
Memory Type
DDR SDRAM
Memory Size
128MB
Speed
200MHz
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
64b
Organization
16Mx64
Total Density
128MByte
Chip Density
256Mb
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
880mA
Number Of Elements
4
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1344
pdf: 09005aef8086ea3d, source: 09005aef8086ea0b
DD4C8_16_32x64HG.fm - Rev. C 9/04 EN
22. The valid data window is derived by achieving
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
25. To maintain a valid level, the transitioning edge of
once every 140.6µs (64MB) or 70.3µs (128MB,
256MB); burst refreshing or posting by the DRAM
controller greater than eight refresh cycles is not
allowed.
other specifications:
(
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55, beyond which functionality is
uncertain. Figure 8, Derating Data Valid Window
(
vided below for duty cycles ranging between 50/
50 and 45/55.
result in a fail value. CKE is HIGH during RE-
FRESH command period (
LOW (i.e., during standby).
t
t
QH =
QH -
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
t
HP -
t
DQSQ), shows derating curves are pro-
50/50
3.750
2.500
t
QHS). The data valid window derates
NA
49.5/50.5
3.700
-335
-262/-26A/-265 @
-262/-26A/-265 @
t
2.463
HP (
t
Figure 8: Derating Data Valid Window
t
CK/2),
RFC [MIN]) else CKE is
49/51
3.650
2.425
t
t
CK = 10ns
CK = 7.5ns
t
DQSQ, and
48.5/52.5
3.600
2.388
(
t
3.550
48/52
t
QH
QH -
2.350
Clock Duty Cycle
20
t
DQSQ)
47.5/53.5
3.500
26. JEDEC specifies CK and CK# input slew rate must
27. DQ and DM input slew rates must not deviate
28. V
29. The clock is allowed up to ±150ps of jitter. Each
2.313
64MB, 128MB, 256MB (x64, SR)
200-PIN DDR SDRAM SODIMM
the input must:
be 1V/ns (2V/ns differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5 V/ns, timing
must be derated: 50ps must be added to
t
slew rate exceeds 4 V/ns, functionality is uncer-
tain. For -335, slew rates must be 0.5 V/ns.
not active while any device bank is active.
timing parameter is allowed to vary by the same
amount.
b. Reach at least the target AC level.
a. Sustain a constant slew rate from the current
c. After the AC target level is reached, continue to
DH for each 100 mv/ns reduction in slew rate. If
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
AC level through to the target AC level, V
or V
maintain at least the target DC level, V
or V
3.450
47/53
must not vary more than 4 percent if CKE is
2.275
IH
IH
(AC).
(DC).
46.5/54.5
3.400
2.238
3.350
46/54
2.200
©2004 Micron Technology, Inc. All rights reserved.
45.5/55.5
3.300
2.163
3.250
45/55
2.125
t
DS and
IL
IL
(DC)
(AC)