MT36LSDT25672G-13EC2 Micron Technology Inc, MT36LSDT25672G-13EC2 Datasheet - Page 8

• Manufacturer Part Number: MT36LSDT25672G-13EC2
• Description: MODULE SDRAM 2GB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36LSDT25672G-13EC2

• Memory Type: SDRAM
• Memory Size: 2GB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Initialization
Mode Register Definition
Burst Length
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
SDRAMs must be powered up and initialized in a predefined manner. Operational pro-
cedures other than those specified may result in undefined operation. Once power is
applied to V
defined as a signal cycling within timing constraints specified for the clock pin), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP . Starting at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands should be
applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All device
banks must then be precharged, thereby placing the device in the all device banks idle
state.
Once in the idle state, two auto refresh cycles must be performed. After the auto refresh
cycles are complete, the SDRAM is ready for mode register programming. Because the
mode register will power up in an unknown state, it should be loaded prior to applying
any operational command.
The mode register is used to define the specific mode of operation of the SDRAM. This
definition includes the selection of a burst length, a burst type, a CAS latency, an operat-
ing mode and a write burst mode, as shown in Figure 4 on page 9. The mode register is
programmed via the LOAD MODE REGISTER command and will retain the stored infor-
mation until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst
(sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the oper-
ating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future
use. Address A12 (M12) is undefined but should be driven LOW during loading of the
mode register.
The mode register must be loaded when all device banks are idle, and the controller
must wait the specified time before initiating the subsequent operation. Violating either
of these requirements will result in unspecified operation.
Read and write accesses to the SDRAM are burst oriented, with the burst length being
programmable, as shown in Figure 4 on page 9. The burst length determines the maxi-
mum number of column locations that can be accessed for a given READ or WRITE
command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and
the interleaved burst types, and a full-page burst is available for the sequential type. The
full-page burst is used in conjunction with the BURST TERMINATE command to gener-
ate arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached, as shown in
Table 6 on page 10. The block is uniquely selected by A1–Ai when BL = 2; A2–Ai when
BL = 4; and by A3–Ai when BL = 8. See Note 8 of Table 6 on page 10 for Ai values. The
remaining (least significant) address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if the boundary is reached, as
shown in Table 6 on page 10.
DD
and V
DD
Q (simultaneously) and the clock is stable (stable clock is
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
Initialization