MT18VDDT6472AG-265G4 Micron Technology Inc, MT18VDDT6472AG-265G4 Datasheet - Page 9

• Manufacturer Part Number: MT18VDDT6472AG-265G4
• Description: MODULE SDRAM DDR 512MB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDT6472AG-265G4

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 266MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.
A3 specifies the type of burst (sequential or inter-
leaved), A4–A6 specify the CAS latency, and A7–A11
(256MB); A7–A12 (512MB and 1GB); or A7–A13 (2GB)
specify the operating mode.
Burst Length
are burst oriented, with the burst length being pro-
grammable, as shown in Figure 5, Mode Register Defi-
nition Diagram.
maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 2, 4, or 8 locations are available for both the
sequential and the interleaved burst types.
known operation or incompatibility with future ver-
sions may result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–Ai (excluding A10, which is assigned
the auto precharge command) when the burst length
is set to two, by A2–Ai when the burst length is set to
four and by A3–Ai when the burst length is set to eight
(where Ai is the most significant column address bit for
a given module configuration. See Note 5 of Table 6,
Burst Definition Table, on page 10, Burst Definition
Table.) The remaining (least significant) address bit(s)
is (are) used to select the starting location within the
block. The programmed burst length applies to both
READ and WRITE bursts.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 10.
pdf: 09005aef808a331f, source: 09005aef80858037
DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN
Reprogramming the mode register will not alter the
Mode register bits A0–A2 specify the burst length,
Read and write accesses to the DDR SDRAM devices
Reserved states should not be used, because un-
When a READ or WRITE command is issued, a block
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
The burst length determines the
256MB, 512MB, 1GB, 2GB (x72, ECC, SR)
9
256MB Module
512MB and 1GB Modules
* M15 and M14 (BA1 and BA0)
* M13 and M12 (BA0 and BA1) must be “0, 0” to select the
* M14 and M13 (BA0 and BA1) must be “0, 0” to select the
2GB Module
0*
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
base mode register (vs. the extended mode register).
base mode register (vs. the extended mode register).
BA1
15
Figure 5: Mode Register Definition
0*
0*
14
BA1
BA0
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0*
0*
13
184-PIN DDR SDRAM RDIMM
13
BA1
BA0
13
A13
0*
12
12
BA0
A12 A11
12
A12 A11
Operating Mode
Operating Mode
11
A11
11
11
M13
Operating Mode
0
0
-
10
10
10
A10
A10
A10
M12 M11
0
0
-
9
9
9
A9
A9
A9
0
0
-
8
A8
8
A8
8
A8
M10
0
0
-
Diagram
7
7
7
A7 A6 A5 A4 A3
A7 A6 A5 A4 A3
A7 A6 A5 A4 A3
M9
CAS Latency BT
M6
CAS Latency BT
0
0
-
CAS Latency BT
0
0
0
0
1
1
1
1
6
6
6
M8 M7
0
1
M5
-
0
0
1
1
0
0
1
1
5
5
5
0
0
-
M4
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0
1
0
1
0
1
0
1
4
4
4
M6-M0
M3
0
1
Valid
Valid
3
3
3
-
Burst Length
Burst Length
Burst Length
M2
2
2
0
0
0
0
1
1
1
1
2
A2 A1 A0
A2 A1 A0
A2 A1 A0
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M1
1
0
0
1
1
0
0
1
1
1
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
1
2.5
2
M0
0
1
0
1
0
1
0
1
0
0
0
Interleaved
Burst Type
Sequential
Burst Length
Mode Register (Mx)
Mode Register (Mx)
Reserved
Reserved
Reserved
Reserved
Reserved
Mode Register (Mx)
M3 = 0
Address Bus
Address Bus
Address Bus
2
4
8