MT18VDDT6472AG-265G4 Micron Technology Inc, MT18VDDT6472AG-265G4 Datasheet
MT18VDDT6472AG-265G4
Specifications of MT18VDDT6472AG-265G4
Related parts for MT18VDDT6472AG-265G4
MT18VDDT6472AG-265G4 Summary of contents
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... ECC, SR) MT18VDDT3272 – 256MB MT18VDDT6472 – 512MB MT18VDDT12872 – 1GB MT18VDDT25672 – 2GB For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 184-Pin DIMM (MO-206) Standard 1.70in. (43.18mm) Low Profile 1.20in. (30.48mm) OPTIONS • Package 184-pin DIMM (standard) 184-pin DIMM (lead-free) • ...
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Table 2: Part Numbers and Timing Parameters 1 PART NUMBER MODULE DENSITY MT18VDDT3272G-262__ 256MB MT18VDDT3272Y-262__ 256MB MT18VDDT3272G-26A__ 256MB 256MB MT18VDDT3272Y-26A__ MT18VDDT3272G-265__ 256MB MT18VDDT3272Y-265__ 256MB MT18VDDT3272G-202__ 256MB 256MB MT18VDDT3272Y-202__ MT18VDDT6472G-262__ 512MB MT18VDDT6472Y-262__ 512MB MT18VDDT6472G-26A__ 512MB MT18VDDT6472Y-26A__ 512MB 512MB MT18VDDT6472G-265__ MT18VDDT6472Y-265__ 512MB ...
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Table 3: Pin Assignment (184-Pin DIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL DQ17 47 REF 2 DQ0 25 DQS2 DQ1 DQS0 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS SYMBOL 10 63, 65, 154 WE#, CAS#, RAS# 137, 138 CK0, CK0# 21 157 52, 59 ...
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Table 5: Pin Descriptions (Continued) Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS SYMBOL 12,13, 19, 20, DQ0–DQ63 23, 24, 28, 31, 33, 35, ...
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... Standard modules use the following DDR SDRAM devices: MT46V32M4TG (256MB); MT46V64M4TG (512MB); MT46V128M4TG (1GB); MT46V256M4TG (2GB) Lead-free modules use the following DDR SDRAM devices: MT46V32M4P (256MB); MT46V64M4P (512MB); MT46V128M4P (1GB); MT46V256M4TG (2GB) Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... REF RESET Standard modules use the following DDR SDRAM devices: MT46V32M4TG (256MB); MT46V64M4TG (512MB); MT46V128M4TG (1GB); MT46V256M4TG (2GB) Lead-free modules use the following DDR SDRAM devices: MT46V32M4P (256MB); MT46V64M4P (512MB); MT46V128M4P (1GB); MT46V256M4TG (2GB) 7 184-PIN DDR SDRAM RDIMM DQS CS# DM DQ4 ...
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... DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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... BA1 A8 BA0 A11 A10 Operating Mode M13 and M12 (BA0 and BA1) must be “0, 0” to select the base mode register (vs. the extended mode register). 512MB and 1GB Modules BA1 A8 BA0 A12 A11 A10 Operating Mode * M14 and M13 (BA0 and BA1) must be “0, 0” to select the base mode register (vs ...
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Table 6: Burst Definition Table ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...
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... DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN 256MB, 512MB, 1GB, 2GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Figure 7: Extended Mode Register Definition Diagram 256MB Module BA1 BA0 A8 A11 A10 Operating Mode 512MB and 1GB Modules A8 BA1 BA0 A12 A11 A10 Operating Mode 2GB Module BA1 BA0 A13 ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 256MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12; notes appear on pages 22–25; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN (MIN); DQ, DM ...
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Table 13: I Specifications and Conditions – 512MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12; notes appear on pages 22–25; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN (MIN); DQ, DM ...
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I Specifications and Conditions – 1GB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12; notes appear on pages 22–25; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN (MIN); DQ, DM and DQS ...
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I Specifications and Conditions – 2GB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12; notes appear on pages 22–25; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN (MIN); DQ, DM and DQS ...
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Table 14: Capacitance Note: 11; notes appear on pages 22–25 PARAMETER Input/Output Capacitance: DQ, DQS Input Capacitance: Command and Address, S#, CKE Input Capacitance:CK, CK# Table 15: Electrical Characteristics and Recommended AC Operating Conditions DDR SDRAM Components Only Notes: 1–5, ...
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Table 15: Electrical Characteristics and Recommended AC Operating Conditions (Continued) DDR SDRAM Components Only AC CHARACTERISTICS PARAMETER PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble ...
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Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions Notes: 1–5, 12–15, 29; notes appear on pages 22–25; 0°C AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time ...
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Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 12–15, 29; notes appear on pages 22–25; 0°C AC CHARACTERISTICS PARAMETER Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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DRAM control- ler greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications CK/2 ...
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READs and WRITEs with auto precharge are not t allowed to be issued until RAS (MIN) can be satis- fied prior to the internal precharge command being issued. 32. Any positive glitch in the nominal voltage must be less ...
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Random address changing and 100 percent of data changing at every transfer. 44. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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Table 17: Register Timing Requirements and Switching Characteristics Note: 1 REGISTER SYMBOL PARAMERTER f Clock Frequency clock t Clock to Output Time pd t Reset to Output Time PHL SSTL (bit t Pulse Duration w pattern) by JESD82 ...
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Table 18: PLL Clock Driver Timing Requirements and Switching Characteristics Note: 1 PARAMETER SYMBOL Operating Clock Frequency Input Duty Cycle Stabilization Time Cycle to Cycle Jitter Static Phase Offset Output Clock Skew Period Jitter Half-Period Jitter t Input Clock Slew ...
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... The component case temperature measurements shown above were obtained experimentally. The typical system to be used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered memory modules. Case temperatures charted represent worst-case component locations on modules installed in the internal slots of the system. ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 13, Data Validity, and Figure ...
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Table 19: EEPROM Device Select Code The most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 20: EEPROM Operating Modes MODE RW BIT Current Address Read Random Address Read ...
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Table 21: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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Table 23: Serial Presence-Detect Matrix – 256MB, 512MB, and 1GB “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 35 BYTE DESCRIPTION 0 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD ...
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Table 23: Serial Presence-Detect Matrix – 256MB, 512MB, and 1GB (Continued) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 35 BYTE DESCRIPTION 29 Minimum RAS# to CAS# Delay, 30 Minimum RAS# Pulse Width, (Note 2) 31 ...
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... The value of RAS used for -262/-26A/-265 modules is calculated from 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini- mum slew rate is met ...
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Table 24: Serial Presence-Detect Matrix – 2GB “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 35 BYTE DESCRIPTION 0 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental ...
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... The value of RAS used for -262/-26A/-265 modules is calculated from 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini- mum slew rate is met ...
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Figure 17: Standard PCB Dimensions U1 U2 0.079 (2.00) R (4X) 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.050 (1.27) TYP. 0.091 (2.30) TYP. U14 U15 PIN 184 NOTE: All dimensions in inches (millimeters); pdf: 09005aef808a331f, source: 09005aef80858037 ...
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Figure 18: Low Profile PCB Dimensions 0.079 (2.00) R (4X 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.050 (1.27) TYP. 0.091 (2.30) 2.55 (64.77) TYP. U10 U11 U12 PIN 184 NOTE: All dimensions in inches ...