MT18VDDT6472AG-265G4 Micron Technology Inc, MT18VDDT6472AG-265G4 Datasheet - Page 15
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MT18VDDT6472AG-265G4
Manufacturer Part Number
MT18VDDT6472AG-265G4
Description
MODULE SDRAM DDR 512MB 184DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT18VDDT12872Y-265D2.pdf
(39 pages)
Specifications of MT18VDDT6472AG-265G4
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
266MT/s
Package / Case
184-DIMM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 13: I
DDR SDRAM components only
Notes: 1–5, 8, 10, 12; notes appear on pages 22–25; 0°C
pdf: 09005aef808a331f, source: 09005aef80858037
DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge;
(MIN);
clock cyle; Address and control inputs changing once every two clock
cycles
OPERATING CURRENT: One device bank; Active-read Precharge; Burst
= 4;
I
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle;
Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
MIN; CKE = HIGH; Address and other control inputs changing once per
clock cycle. V
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;
Power-down mode;
CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge;
t
cycle; Address and other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle;
=
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing once per clock cycle;
t
cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE
OPERATING CURRENT: Four device bank interleaving READs (BL = 4)
with auto precharge,
t
READ, or WRITE commands
OUT
CK =
CK =
CK =
t
CK (MIN); I
t
= 0mA; Address and control inputs changing once per clock cycle
RC =
t
t
t
CK (MIN); Address and control inputs change only during Active
CK (MIN); DQ, DM and DQS inputs changing twice per clock
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
t
CK =
t
RC (MIN);
t
IN
OUT
CK (MIN); DQ, DM and DQS inputs changing once per
= V
DD
= 0mA
REF
t
t
Specifications and Conditions – 512MB
t
CK =
CK =
CK =
t
for DQ, DQS, and DM
RC =
t
RC =
t
t
t
CK (MIN); CKE = (LOW)
CK (MIN);
CK (MIN);
t
RC (MIN);
t
RAS (MAX);
0.2V
t
t
REFC =
REFC = 7.8125µs
256MB, 512MB, 1GB, 2GB (x72, ECC, SR)
t
RFC (MIN)
T
A
t
RC =
t
15
CK =
+70°C; V
t
RC
t
t
CK
CK
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM RDIMM
SYMBOL
I
= V
I
I
I
I
I
I
DD4W
I
I
I
DD3N
DD5A
I
I
DD2P
DD2F
DD3P
DD4R
DD
DD
DD1
DD6
DD7
DD
0
5
Q = +2.5V ±0.2V
2,250
2,880
2,700
2,700
4,230
6,300
-262
810
450
900
108
72
72
MAX
-265/-202 UNITS
-26A/
©2004 Micron Technology, Inc. All rights reserved.
2,160
2,610
2,700
2,700
4,230
6,300
810
450
900
108
72
72
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
21, 28, 44
21, 28, 44
NOTES
20, 42
20, 42
20, 42
24, 44
24, 44
20, 43
45
41
20
9