MT18LSDT6472G-13ED2 Micron Technology Inc, MT18LSDT6472G-13ED2 Datasheet - Page 4
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MT18LSDT6472G-13ED2
Manufacturer Part Number
MT18LSDT6472G-13ED2
Description
MODULE SDRAM 512MB 168DIMM
Manufacturer
Micron Technology Inc
Specifications of MT18LSDT6472G-13ED2
Memory Type
SDRAM
Memory Size
512MB
Speed
133MHz
Package / Case
168-DIMM
Main Category
DRAM Module
Sub-category
SDRAM
Module Type
168RDIMM
Device Core Size
72b
Organization
64Mx72
Total Density
4831838208
Chip Density
256Mb
Access Time (max)
5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Operating Current
2.43A
Number Of Elements
18
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temp Range
0C to 55C
Operating Temperature Classification
Commercial
Pin Count
168
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 6:
PDF: 09005aef809b161a/Source: 09005aef809b15eb
SD18C32_64_128x72.fm - Rev. E 1/08 EN
RAS#, CAS#, WE#
DQMB0–DQMB7
DQ0–DQ63
BA0, BA1
CK0–CK3
SA0–SA2
CB0–CB7
Symbol
S0#, S2#
A0–A12
REGE
CKE0
SDA
V
SCL
V
NC
NF
DD
SS
Pin Descriptions
Output
Output
Output
Supply
Supply
Input/
Input/
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
–
–
Description
Address inputs: Sampled during the ACTIVE and READ/WRITE commands, with A10
defining auto precharge, to select one location out of the memory array in the
respective device bank. A10 is sampled during a PRECHARGE command to determine
whether both device banks are precharged (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE REGISTER command. A0–A11 (256MB) and
A0–A12 (512MB, 1GB).
Bank address inputs: BA0 and BA1 define the device bank to which an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
Clock: CK0 is distributed through an on-board PLL to all devices. CK1–CK3 are
terminated.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) the CK
signal. Deactivating the clock provides power-down and SELF REFRESH operations (all
device banks idle) or CLOCK SUSPEND operation (burst access in progress). CKE is
synchronous except after the device enters power-down and self refresh modes, where
CKE becomes asynchronous until after exiting the same mode. The input buffers,
including CK, are disabled during power-down and self refresh modes, providing low
standby power.
Input/output mask: DQMB is an input mask signal for write accesses and an output
enable signal for read accesses. Input data is masked when DQMB is sampled HIGH
during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock
latency) when DQMB is sampled HIGH during a READ cycle.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Register enable.
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when S# is registered HIGH. S# is considered part
of the command code.
Presence-detect address inputs: These pins are used to configure the presence-
detect device.
Serial clock for presence-detect: SCL is used to synchronize the presence-detect
data transfer to and from the module.
Check bits.
Data input/output: Data bus.
Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses
and data into and data out of the EEPROM portion of the module.
Power supply: +3.3V ±0.3V.
Ground.
Not connected: These pins are not connected on the module.
No function: Connected within the module but provides no functionality.
256MB, 512MB, 1GB (x72, ECC, SR): 168-Pin SDRAM RDIMM
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
©2003 Micron Technology, Inc. All rights reserved