MT18LSDT6472AG-13ED2 Micron Technology Inc, MT18LSDT6472AG-13ED2 Datasheet - Page 21
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MT18LSDT6472AG-13ED2
Manufacturer Part Number
MT18LSDT6472AG-13ED2
Description
MODULE SDRAM 512MB 168DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT18LSDT6472AG-13ED2.pdf
(26 pages)
Specifications of MT18LSDT6472AG-13ED2
Memory Type
SDRAM
Memory Size
512MB
Speed
133MHz
Package / Case
168-DIMM
Main Category
DRAM Module
Sub-category
SDRAM
Module Type
168UDIMM
Device Core Size
72b
Organization
64Mx72
Total Density
512MByte
Chip Density
256Mb
Access Time (max)
5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Operating Current
1.233A
Number Of Elements
18
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temp Range
0C to 65C
Operating Temperature Classification
Commercial
Pin Count
168
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 20: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
Table 21: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
NOTE:
09005aef807b3709
SD9_18C32_64X72AG.fm - Rev. E 11/04 EN
1. To aviod spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: I
INPUT LEAKAGE CURRENT: V
OUTPUT LEAKAGE CURRENT: V
STANDBY CURRENT: SCL = SDA = V
inputs = V
POWER SUPPLY CURRENT:
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
edge of SDA.
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
SS
or V
DD
OUT
SS
SS
IN
= 3mA
; V
; V
= GND to V
OUT
DDSPD
DDSPD
= GND to V
DD
- 0.3V; All other
= +3.3V ±0.3V
= +3.3V ±0.3V
t
WRC) is the time from a valid stop condition of a write sequence to the end of
DD
256MB (x72, ECC, SR), 512MB (x72, ECC, DR)
DD
21
SYMBOL
I
I
CC
CC
V
V
I
V
V
I
CCS
Write
I
LO
Read
DD
OL
LI
IH
IL
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SYMBOL
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STA
SU:STO
t
t
t
t
HIGH
LOW
f
WRC
t
t
BUF
SCL
AA
DH
t
t
t
F
R
I
168-PIN SDRAM UDIMM
V
DD
MIN
-10
-10
-1
3
–
–
–
–
x 0.7
MIN
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
0
V
V
DD
DD
MAX
MAX
300
400
0.9
0.3
3.6
0.4
50
10
10
10
30
3
1
+ 0.5
x 0.3
UNITS
KHz
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
©2004 Micron Technology, Inc.
UNITS
mA
mA
µA
µA
µA
V
V
V
V
NOTES
1
2
2
3
4