MT16LSDF6464HY-133D2 Micron Technology Inc, MT16LSDF6464HY-133D2 Datasheet - Page 16

• Manufacturer Part Number: MT16LSDF6464HY-133D2
• Description: MODULE SDRAM 512MB 144-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16LSDF6464HY-133D2

• Memory Type: SDRAM
• Memory Size: 512MB
• Speed: 133MHz
• Package / Case: 144-SODIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 144SODIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 256Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 1.096A
• Number Of Elements: 16
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 144
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. E 4/06 EN
10.
11. AC timing and I
12. Other input signals can change no more than
13. I
14. Timing actually specified by
15. Timing actually specified by
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. In addition to meeting the transition rate specifi-
9. Outputs measured at 1.5V with equivalent load:
1 MHz, T
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
indicate cycle time at which proper operation
over the full temperature range is ensured (0°C
T
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V
and V
V
AUTO REFRESH-command wake-ups should be
repeated any time the
exceeded.
cation, the clock and CKE must transit between
V
tonic manner.
t
the open circuit condition; it is not a reference to
V
t
with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1ns, then
the timing is referenced at V
(MIN) and no longer at the 1.5V crossover point.
once every two clocks and are otherwise at valid
V
properly initialized.
fied as a reference only at minimum cycle rate.
specified as a reference only at minimum cycle
rate.
HZ defines the time at which the output achieves
OH before going High-Z.
DD
DD
A ≤
OH
SS
IH
IH
and V
or V
and V
+70°C).
is dependent on output loading and cycle
specifications are tested after the device is
or V
DD
IL
OL
A
Q must be powered up simultaneously.
SS
IL
levels.
= 25°C; pin under test biased at 1.4V.
. The last valid data element will meet
Q must be at same potential.) The two
(or between V
DD
Q
tests have V
t
REF refresh requirement is
50pF
t
IL
SS
T = 1ns.
t
.
DD
and V
WR plus
t
CKS; clock(s) speci-
IL
IL
, V
= 0V and V
(MAX) and V
DD
IH
Q = +3.3V; f =
) in a mono-
t
RP; clock(s)
IH
= 3V,
DD
IH
≤
16
16. Timing actually specified by
17. Required clocks are specified by JEDEC function-
18. The I
19. Address transitions average one transition every
20. CLK must be toggled a minimum of two times
21. Based on
22. V
23. The clock frequency must remain constant (stable
24. Auto precharge mode only. The precharge time
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
28. Parameter guaranteed by design.
29. For -10E, CL = 2 and
30. CKE is HIGH during refresh command period
31. Refer to device data sheet for timing waveforms.
32. The value of
33. Leakage number reflects the worst case leakage
ality and are not dependent on any timing param-
eter.
tionally according to the amount of frequency
alteration for the test condition.
two clocks.
during this period.
133 and -13E.
width
than one third of the cycle rate. V
V
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing
be used to reduce the data rate.
(
for -10E after the first clock delay, after the last
WRITE is executed. May not exceed limit set for
precharge mode.
t
and is guaranteed by design.
and
t
actually a nominal value and does not result in a
fail value.
ule SPDs is calculated from
possible through the module pin, not what each
memory device contributes.
AC for -133/-13E at CL = 3 with no load is 4.6ns
RFC (MIN), else CKE is LOW. The I
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
IL
RP) begins at 7ns for -13E; 7.5ns for -133 and 7ns
(MIN) = -2V for a pulse width
t
overshoot: V
WR, and PRECHARGE commands). CKE may
t
CK = 7.5ns; for -13E, CL = 2 and
DD
≤
144-PIN SDRAM SODIMM
3ns, and the pulse width cannot be greater
256MB, 512MB (x64, DR)
current will increase or decrease propor-
t
CK = 10ns for -10E, and
t
RAS used in -13E speed grade mod-
IH
(MAX) = V
t
CK = 10ns; for -133, CL = 3
©2006 Micron Technology, Inc. All rights reserved.
t
RC -
t
WR.
DD
Q + 2V for a pulse
t
≤
RP = 45ns.
t
3ns.
CK = 7.5ns for -
IL
t
CK = 7.5ns.
undershoot:
DD
6 limit is