MT16LSDF6464HG-133D2 Micron Technology Inc, MT16LSDF6464HG-133D2 Datasheet - Page 11

• Manufacturer Part Number: MT16LSDF6464HG-133D2
• Description: MODULE SDRAM 512MB 144SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16LSDF6464HG-133D2

• Memory Type: SDRAM
• Memory Size: 512MB
• Speed: 133MHz
• Package / Case: 144-SODIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 144SODIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 256Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 1.096A
• Number Of Elements: 16
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 144
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Commands
able commands. This is followed by written descrip-
tion of each command. For a more detailed
Table 9:
CKE is HIGH for all commands shown except SELF REFRESH
NOTE:
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. E 4/06 EN
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (select bank and activate row)
READ (select bank and column, and start READ burst)
WRITE (select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(enter self refresh mode)
LOAD MODE REGISTER
Write enable/output enable
Write inhibit/output High-Z
1. A0–A11 (256MB) or A0–A12 (512MB) provide device row address, and BA0, BA1 determine which device bank is made
2. A0–A9 (256MB and 512MB) provide device column address; A10 HIGH enables the auto precharge feature (nonpersis-
3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
6. A0–A11 define the op-code written to the mode register; for the 256MB and 512MB, A12 should be driven low.
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
The Truth Table provides a quick reference of avail-
active.
tent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or
written to.
BA0, BA1 are “Don’t Care.”
Truth Table – SDRAM Commands and DQMB Operation
CS# RAS# CAS# WE# DQMB
H
L
L
L
L
L
L
L
L
–
–
11
description of commands and operations, refer to the
128Mb or 256Mb SDRAM component data sheet.
X
H
H
H
H
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
H
H
H
H
L
L
L
L
–
–
144-PIN SDRAM SODIMM
256MB, 512MB (x64, DR)
X
H
H
H
H
L
L
L
L
–
–
L/H
L/H
H
X
X
X
X
X
X
X
L
8
8
Bank/Row
Bank/Col
Bank/Col
Op-code
ADDR
©2006 Micron Technology, Inc. All rights reserved.
Code
X
X
X
X
–
–
High-Z
Active
Active
Valid
DQ
X
X
X
X
X
X
X
NOTES
4, 5
1
2
2
3
6
7
7