MT9LSDT1672AY-133G3 Micron Technology Inc, MT9LSDT1672AY-133G3 Datasheet - Page 12

• Manufacturer Part Number: MT9LSDT1672AY-133G3
• Description: MODULE SDRAM 128MB 168-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9LSDT1672AY-133G3

• Memory Type: SDRAM
• Memory Size: 128MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168UDIMM
• Device Core Size: 72b
• Organization: 16Mx72
• Total Density: 128MByte
• Chip Density: 128Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 1.35A
• Number Of Elements: 9
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Commands
of available commands. This is followed by written
description of each command. For a more detailed
Table 9:
CKE is HIGH for all commands shown except SELF REFRESH
NOTE:
09005aef807b3709
SD9_18C16_32x72AG.fm - Rev. E 6/04 EN
1. A0–A11 provide row address; BA0–BA1 determine which device bank is made active.
2. A0–A9 provide column address; A10 HIGH enables the auto-precharge feature (nonpersistent), while A10 LOW disables
3. A10 LOW: BA0–BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
6. A0–A11 define the op-code written to the mode register.
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE
burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
The Truth Table, below, provides a quick reference
the auto-precharge feature; BA0–BA1 determine which device bank is being read from or written to.
BA0, BA1 are “Don’t Care.”
SDRAM Commands and DQMB Operation Truth Table
128MB (x72, ECC, SR), 256MB (x72, ECC, DR)
CS# RAS# CAS#
H
L
L
L
L
L
L
L
L
–
–
12
description of commands and operations, refer to the
128Mb SDRAM component data sheet.
X
H
H
H
H
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
X
L
L
L
L
–
–
WE# DQMB
168-PIN SDRAM UDIMM
X
H
H
H
H
L
L
L
L
–
–
L/H
L/H
H
X
X
X
X
X
X
X
L
Bank/Col
Bank/Col
Op-code
ADDR
Bank/
Code
Row
X
X
X
X
–
–
High-Z
©2004 Micron Technology, Inc.
Active
Active
Valid
DQ
X
X
X
X
X
X
X
NOTES
4, 5
1
2
2
3
6
7
7