MT9LSDT1672AY-133G3 Micron Technology Inc, MT9LSDT1672AY-133G3 Datasheet

no-image

MT9LSDT1672AY-133G3

Manufacturer Part Number
MT9LSDT1672AY-133G3
Description
MODULE SDRAM 128MB 168-DIMM
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT9LSDT1672AY-133G3

Memory Type
SDRAM
Memory Size
128MB
Speed
133MHz
Package / Case
168-DIMM
Main Category
DRAM Module
Sub-category
SDRAM
Module Type
168UDIMM
Device Core Size
72b
Organization
16Mx72
Total Density
128MByte
Chip Density
128Mb
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Operating Current
1.35A
Number Of Elements
9
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temp Range
0C to 65C
Operating Temperature Classification
Commercial
Pin Count
168
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SYNCHRONOUS
DRAM MODULE
Features
• PC100- and PC133-compliant
• 168-pin, dual in-line memory module (DIMM)
• Unbuffered, ECC-optimized pinout
• 128MB (16 Meg x 72) and 256MB (32 Meg x 72)
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
• Internal pipelined operation; column address can
• Internal SDRAM banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes Concurrent Auto
• Self Refresh Mode
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)
• Gold edge contacts
Table 1:
Table 2:
09005aef807b3709
SD9_18C16_32x72AG.fm - Rev. E 6/04 EN
MODULE
MARKING
Refresh Count
Device Banks
Device Configuration
Row Addressing
Column Addressing
Module Ranks
edge of system clock
be changed every clock cycle
Precharge, and Auto Refresh Modes
-13E
-133
-10E
FREQUENCY
133 MHz
133 MHz
100 MHz
CLOCK
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
Timing Parameters
Address Table
CL = 2
ACCESS TIME
5.4ns
9ns
CL = 3
5.4ns
7.5ns
SETUP
TIME
2ns
1.5
1.5
128MB (x72, ECC, SR), 256MB (x72, ECC, DR)
HOLD
TIME
1ns
0.8
0.8
128Mb (16 Meg x 8)
4 (BA0, BA1)
4K (A0–A11)
1K (A0–A9)
1
1 (S0, S2)
128MB
NOTE:
MT9LSDT1672A(I) – 128MB
MT18LSDT3272A(I) – 256MB
For the latest data sheet, please refer to the Micron
site:
Options
• Self-Refresh
• Package
• Frequency/CAS Latency
• PCB
Standard 1.375in./34.93mm
Low Profile 1.125in./28.58mm
4K
Standard
Low Power
168-pin DIMM (Standard)
168-pin DIMM (Lead-free)
7.5ns (133 MHz)/CL = 2
7.5ns (133 MHz)/CL = 3
10ns (100 MHz)/CL = 2
Standard (1.375in./34.93mm)
Low-Profile (1.125in./28.58mm) See note on page 2
Figure 1: 168-Pin DIMM (MO–161)
www.micron.com/products/modules
1. Consult Micron for product availability.
168-PIN SDRAM UDIMM
128Mb (16 Meg x 8)
2 (S0, S2; S1, S3)
4 (BA0, BA1)
4K (A0–A11)
1K (A0–A9)
256MB
See note on page 2
4K
©2004 Micron Technology, Inc.
Marking
None
-13E
-10E
-133
L
Y
G
1
1
Web

Related parts for MT9LSDT1672AY-133G3

MT9LSDT1672AY-133G3 Summary of contents

Page 1

... PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) MT9LSDT1672A(I) – 128MB MT18LSDT3272A(I) – 256MB For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 168-Pin DIMM (MO–161) Standard 1.375in./34.93mm Low Profile 1.125in./28.58mm Options • Self-Refresh ...

Page 2

... Table 3: Part Numbers PART NUMBER MT9LSDT1672AG-13E_ MT9LSDT1672AY-13E_ MT9LSDT1672AG-133_ MT9LSDT1672AY-133_ MT9LSDT1672AG-10E_ MT9LSDT1672AY-10E_ MT18LSDT3272AG-13E_ MT18LSDT3272AY-13E_ MT18LSDT3272(L)AG-133_ MT18LSDT3272(L)AY-133_ MT18LSDT3272AG-10E_ MT18LSDT3272AY-10E_ NOTE: Designators for component and PCB revision are the last two characters of each part number Consult factory for current revision codes. Example: MT9LSDT1672G-133B1. 09005aef807b3709 SD9_18C16_32x72AG ...

Page 3

Table 4: Pin Assignment (168-Pin DIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL CB1 DQ0 DQ1 DQ2 DQ3 26 ...

Page 4

Table 6: Pin Descriptions Pin numbers may not correlate with symbols. Refer to the Pin Assignment tables on page 3 for more information PIN NUMBERS 27, 111, 115 42, 79, 125, 163 63, 128 30, 45,114, 129 28, 29, 46, ...

Page 5

Table 6: Pin Descriptions Pin numbers may not correlate with symbols. Refer to the Pin Assignment tables on page 3 for more information PIN NUMBERS 6, 18, 26, 40, 41, 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, ...

Page 6

... BA0 BA1: SDRAMs BA1 Note: 1. All resistor values are 10Ω unless otherwise specified. 2. Per industry standard, Micron modules use various component speed grades as referenced in the module part numbering guide at support/numbering.html. 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) ...

Page 7

... BA0: SDRAMs BA1 BA1: SDRAMs NOTE: 1. All resistor values are 10Ω unless othersise specified. 2. Per industry standard, Micron modules use various component speed grades as referenced in the module part numbering guide at support/numbering.html. 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) ...

Page 8

... SDRAM devices with a synchronous interface (all signals are registered on the positive edge of the clock signals). Read and write accesses to the SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the regis- tration of an ACTIVE command, which is then followed by a READ or WRITE command ...

Page 9

M10 and M11 are reserved for future use. Address A12 (M12) is undefined but should be driven LOW during loading of the mode register. The mode register must be loaded when all device banks are idle, and ...

Page 10

Table 7: Burst Definition Table STARTING BURST COLUMN ORDER OF ACCESSES WITHIN LENGTH ADDRESS TYPE = SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...

Page 11

Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When the burst length programmed via M0- M2 applies to both READ and WRITE bursts; ...

Page 12

Commands The Truth Table, below, provides a quick reference of available commands. This is followed by written description of each command. For a more detailed Table 9: SDRAM Commands and DQMB Operation Truth Table CKE is HIGH for all commands ...

Page 13

Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...

Page 14

Table 12: I Specifications and Conditions – 128MB DD Notes 11, 13; notes appear on page 18; V PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE (MIN) STANDBY CURRENT: ...

Page 15

Table 14: Capacitance – 128MB . Note 2; notes appear on page 18 PARAMETER Input Capacitance: Address and Command Input Capacitance: CK0 Input Capacitance: CK2 Input Capacitance: S0# Input Capacitance: S2# Input Capacitance: CKE Input Capacitance: DQMB0, 2– ...

Page 16

Table 16: Electrical Characteristics and Recommended AC Operating Conditions Notes 11, 31; notes appear on page 18 Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters ACCHARACTERISTICS PARAMETER Access timefrom ...

Page 17

Table 17: AC Functional Characteristics Notes 11, 31; notes appear on page 18 PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup ...

Page 18

Notes 1. All voltages referenced This parameter is sampled MHz 25°C; pin under test biased at 1.4V dependent on output loading and cycle DD rates. Specified values are ...

Page 19

SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7, Data Validity, and Figure ...

Page 20

Table 18: EEPROM Device Select Code The most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 19: EEPROM Operating Modes MODE RW BIT Current Address Read RandomAddressRead Sequential Read ...

Page 21

Table 20: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...

Page 22

Table 22: Serial Presence-Detect Matrix “1”/”0”: Serial data, “driven to HIGH”/”driven to LOW”; V BYTE DESCRIPTION 0 Number of Bytes Used by Micron 1 Total Number of SPD Memory Bytes 2 Memory Type 3 Number of Row Addresses 4 Number ...

Page 23

... Module Serial Number 99-125 Manufacturer-Specific Data (RSVD) 126 System Frequency 127 SDRAM Component & Clock Detail NOTE The value of RAS used for -13E modules is calculated from 09005aef807b3709 SD9_18C16_32x72AG.fm - Rev. E 6/04 EN 128MB (x72, ECC, SR), 256MB (x72, ECC, DR) = +3.3V ±0.3V DD ENTRY (VERSION) 1.5ns (-13E/-133) t ...

Page 24

Figure 11: 168-Pin DIMM Dimensions – Single Rank U1 U2 0.079 (2.00) R (2X) 0.118 (3.00) (2X) 0.118 (3.00) TYP 0.250 (6.35) TYP 0.118 (3.00) TYP 2.625 (66.68) PIN 1 (PIN 85 ON BACKSIDE) 0.079 (2.00) R (2X ...

Page 25

Figure 12: 168-Pin DIMM Dimensions – Low-Profile PCB U1 U2 0.079 (2.00) R (2X) 0.118 (3.00) (2X) 0.118 (3.00) TYP 0.118 (3.00) TYP 2.625 (66.68) PIN 1 U11 U12 PIN 168 0.079 (2.00) R (2X 0.118 (3.00) (2X) ...

Page 26

Data Sheet Designation Released (No Mark): This data sheet contains mini- mum and maximum limits specified over the complete power supply and temperature range for production 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, ...

Related keywords