MT8LSDT3264AY-13ED2 Micron Technology Inc, MT8LSDT3264AY-13ED2 Datasheet - Page 8

• Manufacturer Part Number: MT8LSDT3264AY-13ED2
• Description: MODULE SDRAM 256MB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8LSDT3264AY-13ED2

• Memory Type: SDRAM
• Memory Size: 256MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168UDIMM
• Device Core Size: 64b
• Organization: 32Mx64
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 1.08A
• Number Of Elements: 8
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1300; MT8LSDT3264AY-13ED2

General Description
Serial Presence-Detect Operation
Initialization
PDF: 09005aef807b3771/Source: 09005aef807b37b5
SD8_16C32_64x64AG.fm - Rev. D 3/05 EN
The MT8LSDT3264A and MT16LSDT6464A are high-speed CMOS, dynamic random-
access, 256MB and 512MB memory modules organized in a x64 configuration. These
modules use internally configured quad-bank SDRAMs with a synchronous interface (all
signals are registered on the positive edge of the clock signals CK).
Read and write accesses to the SDRAM modules are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1
select the device bank, A0–A11 select the device row). The address bits registered coinci-
dent with the READ or WRITE command are used to select the starting column location
for the burst access.
The modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An AUTO PRECHARGE func-
tion may be enabled to provide a self-timed row precharge that is initiated at the end of
the burst sequence.
SDRAM modules use an internal pipelined architecture to achieve high-speed opera-
tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one device bank while accessing one of the other three
device banks will hide the precharge cycles and provide seamless, high-speed, random-
access operation.
SDRAM modules are designed to operate in 3.3V, low-power memory systems. An auto
refresh mode is provided, along with a power-saving, power-down mode. All inputs and
outputs are LVTTL-compatible.
SDRAM modules offer substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic column-
address generation, the ability to interleave between internal banks in order to hide pre-
charge time and the capability to randomly change column addresses on each clock
cycle during a burst access. For more information regarding SDRAM operation, refer to
the 256Mb SDRAM component data sheets.
SDRAM modules incorporate serial presence-detect (SPD). The SPD function is imple-
mented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes.
The first 128 bytes can be programmed by Micron to identify the module type and vari-
ous SDRAM organizations and timing parameters. The remaining 128 bytes of storage
are available for use by the customer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device (DIMM) occur via a standard I
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on
the module, permanently disabling hardware write protect.
SDRAMs must be powered up and initialized in a predefined manner. Operational pro-
cedures other than those specified may result in undefined operation. Once power is
applied to V
defined as a signal cycling within timing constraints specified for the clock pin), the
DD
256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM
and V
DD
Q (simultaneously) and the clock is stable (stable clock is
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2003 Micron Technology, Inc. All rights reserved.
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