TC58V64BDC Toshiba, TC58V64BDC Datasheet
TC58V64BDC
Specifications of TC58V64BDC
Related parts for TC58V64BDC
TC58V64BDC Summary of contents
Page 1
... The data stored in the TC58V64BDC needs to comply with the data format standardized by the SSFDC Forum in order to maintain compatibility with other SmartMedia ...
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... Status register Address register Address register Command register Command register Control circuit Control circuit HV generator HV generator PARAMETER PARAMETER CONDITION OUT TC58V64BDC Column buffer Column buffer Column decoder Column decoder Data register Data register Sense amp Sense amp Memory cell array Memory cell array ...
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... OUT mA OUT cycle = cycle = cycle ¾ ¾ 0 -400 2 0.4 V pin TC58V64BDC MIN TYP. MAX ¾ 1014 1024 MIN TYP. MAX 3.0 3.3 3.6 ¾ + 0.3 2 -0.3* ¾ 0.8 MIN TYP. MAX ¾ ¾ ±10 ¾ ¾ ± cycle ¾ ¾ ¾ ...
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... CE High to Ready (When interrupted Read Mode) CRY t Device Reset Time (Read/Program/Erase) RST AC TEST CONDITIONS PARAMETER Input level Input pulse rise and fall time Input comparison level Output data comparison level Output load PARAMETER TC58V64BDC MIN MAX UNIT ¾ ¾ ¾ ¾ ...
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... Refer to Application Note (11) toward the end of this document. is greater than or equal to 100 ns. If the CEH signal stays Ready. t CEH 526 527 A Busy MIN ¾ 200 to 300 ¾ ¾ TC58V64BDC pin. ³ 100 ® Busy signal is not A output. t CRY TYP. MAX UNIT ...
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... TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE I/O1 to I/O8 Command Input Cycle Timing Diagram CLE t CLS ALS ALE I/O1 to I/O8 Setup Time CLH ALH TC58V64BDC Hold Time 2001-10-24 6/33 ...
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... Address Input Cycle Timing Diagram t CLS CLE ALS ALE I/O1 to I/O8 Data Input Cycle Timing Diagram CLE CE t ALS ALE WE I/ A16 TC58V64BDC ALH A17 to A22 : CLH 527 2001-10-24 7/33 ...
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... Serial Read Cycle Timing Diagram REA I/ Status Read Cycle Timing Diagram CLE t CLS I/ 70H represents the hexadecimal number REH RHZ REA RHZ t CLS t CLH WHC CSTO t WHR 70H* TC58V64BDC CHZ REA RHZ t CHZ RSTO RHZ Status output : 2001-10-24 8/33 ...
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... ALH ALS ALE I/O1 00H I/O8 Column address Read Operation using 00H Command 255 ALH AR2 A16 A17toA22 ALH AR2 A16 A17toA22 TC58V64BDC REA OUT OUT OUT OUT 527 : CHZ REA RHZ OUT OUT OUT 2001-10-24 9/33 t CEH t CRY t RB ...
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... DS DH I/O1 50H to I/ Read Operation using 50H Command N: 0 to15 t ALS ALH A16 A17toA22 Column address N* t ALS ALH A16 A17toA22 Column address N* TC58V64BDC t AR2 REA OUT OUT OUT 256 + M 256 + 527 : AR2 REA OUT OUT OUT 512 + M 512 + 527 ...
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... Column address Sequential Read (2) Timing Diagram CLE CE WE ALE RE I/O1 01H A16 A17toA22 to I/O8 Column address Page t R address M Page M access Page t 256 + 256 + 256 + R address Page M access TC58V64BDC 527 527 t R Page access : 527 527 t R Page access : 2001-10-24 11/33 ...
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... Sequential Read (3) Timing Diagram CLE CE WE ALE RE I/O1 50H A16 A17toA22 to I/O8 Column address Page t 512 + 512 + 512 + R address Page M access TC58V64BDC 527 512 513 514 527 t R Page access : 2001-10-24 12/33 ...
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... Auto Block Erase Setup command t ALH t ALS not input data while data is being output ALH WB D0H Erase Start command : not input data while data is being output TC58V64BDC t PROG 10H 70H 527 BERASE Status 70H output Status Read Busy command 2001-10-24 13/ Status output ...
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... ID Read Operation Timing Diagram CLE t CLS ALH ALE I/O1 90H to I/O8 t CLS ALS ALH AR1 t 00 Address input TC58V64BDC t REAID REAID 98H E6H Maker code Device code : 2001-10-24 14/33 ...
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... after completion of the operation. The output buffer for this signal is an open drain. Low Voltage Detect: LVD The LVD signal is used to detect the power supply voltage level L), such as during a Program or Erase operation, and will not enter REA TC58V64BDC CLE ALE WE WP ...
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... Table 1. 8I/O I/O6 I/O5 I/O4 I/O3 I/ A14 A13 A12 A11 A10 A22 A21 A20 A19 A18 CLE ALE TC58V64BDC I/O1 A0~A7: Column address A9~A22: Page address A0 A13~A22: Block address A9 A9~A12: NAND address in block A17 0V/V 2001-10-24 16/ ...
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... Table 4. Read mode operation states CLE Output Select L Output Deselect Second Cycle Acceptable while Busy ¾ ¾ ¾ ¾ ¾ Q ¾ D0 ¾ Q ¾ ALE TC58V64BDC HEX data bit assignment (Example) Serial data input: 80H I/ I/O1 I/O1~I/O8 Power L Data output Active H High impedance Active 2001-10-24 17/33 ...
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... The operation of the device after input of the 01H command is the same as that of Read mode (1). If the start pointer set after column address 256, use Read mode (2). However, for a Sequential Read, output of the next page Cell array starts from column address 0. TC58V64BDC 2001-10-24 18/33 ...
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... A4-to-A7 address. (An 00H command is necessary to move the pointer back to the 0-to-511 main memory cell location.) Data output t R Busy 527 (01H) A Sequential Read (2) TC58V64BDC Data output Busy Busy (50H) 512 527 A Sequential Read (3) ...
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... Device Device 2 3 Busy 70H Status on Device 1 Figure 6. Status Read timing application example pin signals from multiple devices are wired together as shown in the TC58V64BDC The Pass/Fail status on I/O1 is only valid when the device is in the Ready state Device Device Status on Device N ...
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... After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. D0 Busy TC58V64BDC Pass 70 I/O Status Read Fail command ...
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... BY The second FF (max 10 ms) t RST FF FF (max 6 ms) t RST command is invalid, but the third TC58V64BDC 00 00 (max 500 ms) t RST Figure 10. 00 Figure 11. I/O status: Pass/Fail ® Pass Ready/Busy ® Ready I/O status: Ready/Busy ® Busy Figure 12. ( command is 2001-10-24 22/33 Figure 8 ...
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... Table 6. Code table I/O8 I/O7 Maker code 1 0 Device code AR1 t REAID 98H Maker code , t and t refer to the AC Characteristics. REAID CR AR1 Figure13. ID Read timing I/O6 I/O5 I/O4 I/ TC58V64BDC E6H Device code I/O2 I/O1 Hex Data 0 0 98H 1 0 E6H 2001-10-24 23/33 ...
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... Command other than “10H” or “FFH” reaches 2.7 V and CE signal is kept high Operation Figure 15. Power-on/off Sequence becomes 2 recommends starting access after about CC FF Reset Figure 16. 10 For this operation the “FFH” command is Programming cannot be TC58V64BDC Don’t care V IL 2001-10-24 24/33 ...
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... However, when the Read command “00H” is input during [A], Status mode is reset and the device returns to Read mode. In this case, data output starts automatically from address N and address input is unnecessary 70 Status Read command input Status Read Figure 18. TC58V64BDC 00 [A] Status output 2001-10-24 25/33 ...
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... C area C area Add Start point B area A area Add DIN Start point C Area Add DIN Start point B Area Figure 20. Example of How to Set the Pointer TC58V64BDC 255 256 511 512 A B Pointer control Figure 19. Pointer control 50H Add Start point C area 00H Add ...
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... V CC Device V SS Figure 21. This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value Ready 1 TC58V64BDC buffer consists of an open drain 3.0 V Busy 1 3 25° 100 2001-10-24 27/ ...
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... The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN (100 ns min) WW Disable Programming WE DIN (100 ns min) WW Enable Erasing WE DIN (100 ns min) WW Disable Erasing WE DIN (100 ns min TC58V64BDC 2001-10-24 28/33 ...
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... Although the device may read in a fourth address ignored inside the chip. Read operation CLE CE WE ALE I/O 00H, 01H, 50H Internal read operation starts when WE goes High in the third cycle. Program operation CLE CE WE ALE I/O 80H Address input Figure 22. Address input Ignored Figure 23. TC58V64BDC Ignored Data input 2001-10-24 29/33 ...
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... Busy state. (Refer to Figure 25.) I/O 00H/01H/50H Hence the RE clock input must start after the address input. All 1s Data Pattern 2 All 1s Data Pattern 2 Figure 24. Address input Figure 25. TC58V64BDC All 1s Data Pattern 5 Data Pattern 5 2001-10-24 30/33 ...
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... When an error happens in Block A, try to reprogram the data into another (Block B) by loading from an external buffer. Then, prevent Block A further system accesses to Block A (by creating a bad block table or by using an another appropriate scheme). Block B Figure 27. TC58V64BDC TYP. MAX UNIT ¾ 1024 Block TM . ...
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... Some electrical specifications in this data sheet show differences from the Forum’s electrical specification. Complying with the Forum’s electrical specification maintains compatibility with other SmartMedias. Please refer following SSFDC Forum’s URL to get the detailed information of each specification. URL http://www.ssfdc.or. especially with large capacity SmartMedia TC58V64BDC small removable TM . 2001-10-24 32/33 ...
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... PACKAGE DIMENSIONS Weight: 1.8 g (typ.) TC58V64BDC 2001-10-24 33/33 ...