HCPL-4661 Avago Technologies US Inc., HCPL-4661 Datasheet - Page 14
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HCPL-4661
Manufacturer Part Number
HCPL-4661
Description
OPTOCPLR 2CH LOG-OUT 10MBD 8-DIP
Manufacturer
Avago Technologies US Inc.
Datasheet
1.HCPL-0600-500E.pdf
(22 pages)
Specifications of HCPL-4661
Voltage - Isolation
5000Vrms
Number Of Channels
2, Unidirectional
Current - Output / Channel
50mA
Data Rate
10MBd
Propagation Delay High - Low @ If
50ns @ 7.5mA
Current - Dc Forward (if)
20mA
Input Type
DC
Output Type
Open Collector
Mounting Type
Through Hole
Package / Case
8-DIP (0.300", 7.62mm)
No. Of Channels
2
Isolation Voltage
3.75kV
Optocoupler Output Type
Logic Gate
Input Current
15mA
Output Voltage
7V
Opto Case Style
DIP
No. Of Pins
8
Propagation Delay Low-high
100ns
Common Mode Voltage Vcm
1000V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
516-1092-5
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Package Characteristics
All Typicals at T
*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0°C to 70°C. Avago specifies -40°C to 85°C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous volt-
age rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equipment
level safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage. ”
†For 6N137, HCPL-2601/2611/2630/2631/4661 only.
Notes:
10. The t
11. The t
12. t
13. See application section titled “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
14. The t
15. The t
16. CM
17. CM
18. For sinusoidal voltages, (|dV
19. No external pull up is required for a high logic state on the enable input. If the V
20. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
21. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V rms for one second (leakage detection
22. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for one second (leakage detection
23. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only.
24. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only
14
1. Each channel.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 20 mA.
3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 15 mA.
4. Derate linearly above 80°C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package.
5. Bypassing of the power supply line is required, with a 0.1 μF ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure 17. Total
6. The JEDEC registration for the 6N137 specifies a maximum I
7. The JEDEC registration for the 6N137 specifies a maximum I
8. The JEDEC registration for the 6N137 specifies a maximum I
9. The JEDEC registration for the 6N137 specifies a maximum I
Parameter
Input-Output
Insulation
Input-Output
Momentary With-
stand Voltage**
Input-Output
Resistance
Input-Output
Capacitance
Input-Input
Insulation
Leakage Current
Resistance
(Input-Input)
Capacitance
(Input-Input)
lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
output pulse.
output pulse.
of the output pulse.
of the output pulse.
performance. For single channel products only.
current limit, I
5-2 Insulation Characteristics Table, if applicable.
current limit, I
5-2 Insulation Characteristics Table, if applicable.
PSK
is equal to the worst case difference in t
H
L
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., V
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., V
ELH
EHL
PLH
PHL
enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the rising edge
enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the falling edge
propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the
propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the
I-O
I-O
A
≤ 5 PA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN 60747-
≤ 5 PA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN 60747-
= 25°C.
Sym.
I
V
R
C
R
C
I-O
I
ISO
I-O
I-O
I-I
I-I
I-I
*
CM
| / dt)
Single 8-Pin DIP
8-Pin DIP, SO-8
8-Pin DIP, SO-8
8-Pin DIP, SO-8
Dual 8-Pin DIP
Dual Channel
Dual Channel
Single SO-8
Widebody
Widebody
Widebody
Dual SO-8
max
OPT 020†
Package
= Sf
CM
PHL
V
and/or t
CM
(p-p).
3750
5000
5000
PLH
Min.
10
10
that will be seen between units at any given temperature and specified test conditions.
12
11
OH
CCH
CCL
EL
of –2.0 mA. Avago guarantees a maximum I
of 250 μA. Avago guarantees a maximum I
of 18 mA. Avago guarantees a maximum I
of 15 mA. Avago guarantees a maximum I
0.005
0.03
0.25
10
10
10
Typ.
0.6
0.5
12
13
11
Max.
0.6
1
V rms
Units
E
PA
PA
pF
pF
:
:
pin is not used, tying V
45% RH, t = 5 s,
V
RH ≤ 50%, t = 1 min,
T
T
T
f = 1 MHz, T
RH ≤ 45%, t = 5 s,
V
f = 1 MHz
A
A
A
I-O
I-I
= 25°C
= 25°C
= 100°C
= 500 V
= 3 kV dc, T
Test Conditions
CCL
A
OH
CCH
EL
= 25°C
of 100 PA.
of 13 mA.
of -1.6 mA.
of 10 mA.
A
V
= 25°C
I-O
E
to V
= 500 V dc
CC
will result in improved CMR
Fig.
O
< 0.8 V).
O
> 2.0 V).
20, 21
20, 21
20, 22
1, 20,
1, 20,
Note
23
23
24
24
24