HCPL-0708-560E Avago Technologies US Inc., HCPL-0708-560E Datasheet - Page 10

• Manufacturer Part Number: HCPL-0708-560E
• Description: OPTOCOUPLER 15MBD VDE 8-SOIC
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL-0708-560E

• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Voltage - Isolation: 3750Vrms
• Number Of Channels: 1, Unidirectional
• Current - Output / Channel: 2mA
• Data Rate: 15MBd
• Propagation Delay High - Low @ If: 35ns @ 12mA
• Current - Dc Forward (if): 20mA
• Input Type: DC
• Output Type: Push-Pull, Totem-Pole
• Mounting Type: Surface Mount
• Isolation Voltage: 3750 Vrms
• Maximum Continuous Output Current: 2 mA
• Maximum Fall Time: 25 ns
• Maximum Forward Diode Current: 20 mA
• Maximum Rise Time: 20 ns
• Minimum Forward Diode Voltage: 1.3 V
• Output Device: Logic Gate Photo IC
• Configuration: 1 Channel
• Maximum Baud Rate: 15 MBps
• Maximum Forward Diode Voltage: 1.8 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Application Information
Bypassing and PC Board Layout
The HCPL-0708 optocoupler is extremely easy to use. No
external interface circuitry is required because the HCPL-
0708 uses high-speed CMOS IC technology allowing
CMOS logic to be connected directly to the inputs and
outputs.
Figure 6. Recommended printed circuit board layout.
Figure 7. Recommended printed circuit board layout.
Propagation Delay, Pulse-Width Distortion and Propagation
Delay Skew
Propagation Delay is a figure of merit which describes
how quickly a logic signal propagates through a sys-
tem. The propagation delay from low to high (t
amount of time required for an input signal to propagate
to the output, causing the output to change from low
10
INPUT
OUTPUT
Figure 8.
I
I
F
F
V
I
O
F
10%
C1, C2 = 0.01 µF TO 0.1 µF
1
2
3
4
90%
t
PLH
8
7
6
5
t
PHL
NC
90%
C2
GND
C1, C2 = 0.01 µF TO 0.1 µF
C
50%
10%
V
V
DD
O
PLH
12 mA
0 mA
V
2.5 V CMOS
V
OH
OL
) is the
V
V
GND
DD
O
As shown in Figure 6, the only external component re-
quired for proper operation is the bypass capacitor. Ca-
pacitor values should be between 0.01 µF and 0.1 µF. For
each capacitor, the total lead length between both ends
of the capacitor and the power-supply pins should not
exceed 20 mm. Figure 7 illustrates the recommended
printed circuit board layout for the HPCL-0708.
to high. Similarly, the propagation delay from high to
low (t
signal to propagate to the output, causing the output to
change from high to low. See Figure 8.
PHL
) is the amount of time required for the input