LTC3728EG Linear Technology, LTC3728EG Datasheet - Page 15

IC SW REG SYNC STP-DN DUAL28SSOP

LTC3728EG

Manufacturer Part Number
LTC3728EG
Description
IC SW REG SYNC STP-DN DUAL28SSOP
Manufacturer
Linear Technology
Series
PolyPhase®r
Type
Step-Down (Buck)r
Datasheet

Specifications of LTC3728EG

Internal Switch(s)
No
Synchronous Rectifier
Yes
Number Of Outputs
2
Voltage - Output
0.8 ~ 5.5 V
Current - Output
3A
Frequency - Switching
250kHz ~ 550kHz
Voltage - Input
3.5 ~ 36 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power - Output
-

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APPLICATIONS INFORMATION
Figure 1 on the fi rst page is a basic LTC3728 application
circuit. External component selection is driven by the
load requirement, and begins with the selection of R
and the inductor value. Next, the power MOSFETs and
D1 are selected. Finally, C
circuit shown in Figure 1 can be confi gured for operation
up to an input voltage of 28V (limited by the external
MOSFETs).
R
R
LTC3728 current comparator has a maximum threshold
of 75mV/R
SGND to 1.1(INTV
sets the peak of the inductor current, yielding a maximum
average output current I
half the peak-to-peak ripple current, ΔI
Allowing a margin for variations in the LTC3728 and external
component values yields:
Because of possible PCB noise in the current sensing loop,
the AC current sensing ripple of ΔV
also needs to be checked in the design to get good sig-
nal-to-noise ratio. In general, for a reasonable good PCB
layout, a 15mV ΔV
conservative number to start with.
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to the
internal compensation required to meet stability criterion
for buck regulators operating at greater than 50% duty
factor. A curve is provided to estimate this reduction in
peak output current level depending upon the operating
duty factor.
Operating Frequency
The LTC3728 uses a constant-frequency, phase-lockable
architecture with the frequency determined by an internal
capacitor. This capacitor is charged by a fi xed current plus
an additional current which is proportional to the voltage
applied to the PLLFLTR pin. Refer to Phase-Locked Loop
SENSE
SENSE
R
SENSE
is chosen based on the required output current. The
Selection for Output Current
=
SENSE
50mV
I
MAX
and an input common mode range of
CC
SENSE
). The current comparator threshold
MAX
voltage is recommended as a
IN
equal to the peak value less
and C
OUT
SENSE
L
are selected. The
.
= ΔI • R
SENSE
SENSE
and Frequency Synchronization in the Applications Infor-
mation section for additional information.
A graph for the voltage applied to the PLLFLTR pin vs
frequency is given in Figure 5. As the operating frequency
is increased the gate charge losses will be higher, reducing
effi ciency (see Effi ciency Considerations). The maximum
switching frequency is approximately 550kHz.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is effi ciency. A higher
frequency generally results in lower effi ciency because
of MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current ΔI
inductance or frequency and increases with higher V
Accepting larger values of ΔI
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ΔI
I
L
=
Figure 5. PPLFLTR Pin Voltage vs Frequency
(f)(L)
1
2.5
2.0
1.5
1.0
0.5
0
200
V
OUT
250
OPERATING FREQUENCY (kHz)
1–
300
V
L
V
350
OUT
=0.3(I
IN
400
L
L
MAX
allows the use of low
decreases with higher
450
) or higher for good
LTC3728
500
3728 F05
550
15
3728fg
IN
:

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