LTC3728EG Linear Technology, LTC3728EG Datasheet - Page 11

• Manufacturer Part Number: LTC3728EG
• Description: IC SW REG SYNC STP-DN DUAL28SSOP
• Manufacturer: Linear Technology
• Series: PolyPhase®r
• Type: Step-Down (Buck)r

Specifications of LTC3728EG

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.8 ~ 5.5 V
• Current - Output: 3A
• Frequency - Switching: 250kHz ~ 550kHz
• Voltage - Input: 3.5 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

OPERATION
Main Control Loop
The LTC3728 uses a constant-frequency, current mode
step-down architecture with the two controller channels
operating 180 degrees out of phase. During normal opera-
tion, each top MOSFET is turned on when the clock for
that channel sets the RS latch, and turned off when the
main current comparator, I1, resets the RS latch. The peak
inductor current at which I1 resets the RS latch is controlled
by the voltage on the I
error amplifi er EA. The V
feedback signal, which is compared to the internal refer-
ence voltage by the EA. When the load current increases,
it causes a slight decrease in V
reference, which in turn causes the I
until the average inductor current matches the new load
current. After the top MOSFET has turned off, the bottom
MOSFET is turned on until either the inductor current
starts to reverse, as indicated by current comparator I2,
or the beginning of the next cycle.
The top MOSFET drivers are biased from fl oating bootstrap
capacitor C
cycle through an external diode when the top MOSFET
turns off. As V
loop may enter dropout and attempt to turn on the top
MOSFET continuously. The dropout detector detects this
and forces the top MOSFET off for about 400ns every tenth
cycle to allow C
The main control loop is shut down by pulling the RUN/
SS pin low. Releasing RUN/SS allows an internal 1.2μA
current source to charge soft-start capacitor C
C
the I
maximum value. As C
pin voltage is gradually released allowing normal, full-
current operation. When both RUN/SS1 and RUN/SS2
are low, all LTC3728 controller functions are shut down,
including the 5V and 3.3V regulators.
Low Current Operation
The FCB pin is a multifunction pin providing two func-
tions: 1) to provide regulation for a secondary winding
by temporarily forcing continuous PWM operation on
both controllers; and 2) select between two modes of
SS
reaches 1.5V, the main control loop is enabled with
TH
voltage clamped at approximately 30% of its
B
, which normally is recharged during each off
IN
B
decreases to a voltage close to V
to recharge.
TH
(Refer to Functional Diagram)
SS
pin, which is the output of each
OSENSE
continues to charge, the I
OSENSE
pin receives the voltage
TH
relative to the 0.8V
voltage to increase
SS
OUT
. When
, the
TH
low current operation. When the FCB pin voltage is below
0.8V, the controller forces continuous PWM current mode
operation. In this mode, the top and bottom MOSFETs
are alternately turned on to maintain the output voltage
independent of direction of inductor current. When the
FCB pin is below V
the controller enters Burst Mode operation. Burst Mode
operation sets a minimum output current level before
inhibiting the top switch and turns off the synchronous
MOSFET(s) when the inductor current goes negative. This
combination of requirements will, at low currents, force
the I
inhibit turn-on of both output MOSFETs until the output
voltage drops. There is 60mV of hysteresis in the burst
comparator B tied to the I
output signals to the MOSFETs that turn them on for several
cycles, followed by a variable “sleep” interval depending
upon the load current. The resultant output voltage ripple
is held to a very small value by having the hysteretic
comparator after the error amplifi er gain block.
Frequency Synchronization
The phase-locked loop allows the internal oscillator to
be synchronized to an external source via the PLLIN pin.
The output of the phase detector at the PLLFLTR pin is
also the DC frequency control input of the oscillator that
operates over a 250kHz to 550kHz range corresponding
to a DC voltage input from 0V to 2.4V. When locked, the
PLL aligns the turn on of the top MOSFET to the rising
edge of the synchronizing signal. When PLLIN is left
open, the PLLFLTR pin goes low, forcing the oscillator to
minimum frequency.
Constant-Frequency Operation
When the FCB pin is tied to INTV
tion is disabled and the forced minimum output current
requirement is removed. This provides constant-frequency,
discontinuous (preventing reverse inductor current)
current operation over the widest possible output current
range. This constant-frequency operation is not as effi cient
as Burst Mode operation, but does provide a lower noise,
constant-frequency operating mode down to approximately
1% of designed maximum output current.
TH
pin below a voltage threshold that will temporarily
INTVCC
TH
pin. This hysteresis produces
– 1V but greater than 0.8V,
CC
, Burst Mode opera-
LTC3728
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3728fg