ADP3209DJCPZ-RL ON Semiconductor, ADP3209DJCPZ-RL Datasheet - Page 24

• Manufacturer Part Number: ADP3209DJCPZ-RL
• Description: IC CTLR BUCK 5BIT 1PH 32LFCSP
• Manufacturer: ON Semiconductor

Specifications of ADP3209DJCPZ-RL

• Applications: Controller, Power Supplies for Next-Generation Intel Processors
• Voltage - Input: 3.3 ~ 22 V
• Number Of Outputs: 1
• Voltage - Output: 0.4 ~ 1.25 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Output Voltage: 1.174 V
• Output Current: 15 A
• Input Voltage: 19 V
• Supply Current: 5 mA
• Switching Frequency: 390 KHz
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Set the AC Load Line
7. Measure the output ripple with no load and with a
1. Remove the dc load from the circuit and connect a
2. Connect the scope to the output voltage and set it to
3. Set the dynamic load for a transient step of about
4. Measure the output waveform (note that use of a
5. The resulting waveform will be similar to that
6. If the difference between V
7. Repeat Steps 5 and 6 until no adjustment of C
8. Set the dynamic load step to its maximum step size
full load with scope, making sure both are within
the specifications.
dynamic load.
dc coupling mode with a time scale of 100 ms/div.
40 A at 1 kHz with 50% duty cycle.
dc offset on the scope may be necessary to see the
waveform). Try to use a vertical scale of
100 mV/div or finer.
shown in Figure 28. Use the horizontal cursors to
measure V
Figure 28. Do not measure the undershoot or
overshoot that occurs immediately after the step.
more than a couple of millivolts, use Equation 47
to adjust C
parallel values to obtain an adequate one because
there are limited standard capacitor values
available (it is a good idea to have locations for
two capacitors in the layout for this reason).
needed. Once this is achieved, do not change C
for the rest of the procedure.
(but do not use a step size that is larger than
needed) and verify that the output waveform is
square, meaning V
C
Figure 28. AC Load Line Waveform
CS(NEW)
ACDRP
CS
+ C
. It may be necessary to try several
CS(OLD)
and V
ACDRP
DCDRP
and V
V
V
V
ACDRP
ACDRP
ACDRP
DCDRP
, as shown in
DCDRP
and V
V
DCDRP
are equal.
DCDRP
(eq. 47)
http://onsemi.com
CS
CS
is
is
24
Set the Initial Transient
Figure 29. Transient Setting Waveform, Load Step
9. Ensure that the load step slew rate and the
1. With the dynamic load set at its maximum step
2. If both overshoots are larger than desired, try the
3. For load release (see Figure 30), if V
power−up slew rate are set to ~150 A/ms to 250
A/ms (for example, a load step of 50 A should take
200 ns to 300 ns) with no overshoot. Some
dynamic loads have an excessive overshoot at
power−up if a minimum current is incorrectly set
(this is an issue if a VTT tool is in use).
size, expand the scope time scale to 2 ms/div to
5 ms/div. This results in a waveform that may have
two overshoots and one minor undershoot before
achieving the final desired value after V
(see Figure 29).
following adjustments in the order shown.
a. Increase the resistance of the ramp resistor
(R
b. For V
switching frequency.
c. For V
C
If these adjustments do not change the response, it
is because the system is limited by the output
decoupling. Check the output response and the
switching nodes each time a change is made to
ensure that the output decoupling is stable.
larger than the value specified by IMVP−6+, a
greater percentage of output capacitance is needed.
Either increase the capacitance directly or decrease
the inductor values. (If inductors are changed,
however, it will be necessary to redesign the
circuit using the information from the spreadsheet
and to repeat all tuning guide procedures).
A
V
RAMP
TRAN1
by 25%.
) by 25%.
TRAN1
TRAN2
V
TRAN2
, increase C
, increase R
V
DROOP
B
A
or increase the
by 25% and decrease
TRANREL
DROOP
is