NCP5210MNR2G ON Semiconductor, NCP5210MNR2G Datasheet

IC CTLR PWM/DDR DUAL BUCK 20-DFN

NCP5210MNR2G

Manufacturer Part Number
NCP5210MNR2G
Description
IC CTLR PWM/DDR DUAL BUCK 20-DFN
Manufacturer
ON Semiconductor
Datasheet

Specifications of NCP5210MNR2G

Applications
Controller, DDR
Voltage - Input
4.5 ~ 13.2 V
Number Of Outputs
3
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-TFQFN Exposed Pad
Output Current
2 A
Switching Frequency
500 KHz
Operating Temperature Range
0 C to + 70 C
Mounting Style
SMD/SMT
Duty Cycle (max)
100 %
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Output
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
NCP5210MNR2G
NCP5210MNR2GOSTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NCP5210MNR2G
Manufacturer:
MAXIM
Quantity:
68
Part Number:
NCP5210MNR2G
Manufacturer:
ON/安森美
Quantity:
20 000
NCP5210
3−in−1 PWM Dual Buck
and Linear DDR Power
Controller
Controller, is a complete power solution for MCH and DDR memory.
This IC combines the efficiency of PWM controllers for the VDDQ
supply and the MCH core supply voltage with the simplicity of linear
regulator for the VTT termination voltage.
four external N−Ch FETs to form the DDR memory supply voltage
(VDDQ) and the MCH regulator. The DDR memory termination
regulator (VTT) is designed to track at the half of the reference voltage
with sourcing and sinking current.
monitoring of 5VDUAL and BOOT voltage, and thermal shutdown.
The device is housed in a thermal enhanced space−saving
QFN−20 package.
Features
Applications
*For additional information on our Pb−Free strategy and soldering details, please
January, 2005 − Rev. 4
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
The NCP5210, 3−in−1 PWM Dual Buck and Linear DDR Power
This IC contains two synchronous PWM buck controller for driving
Protective features include, soft−start circuitry, undervoltage
VMCH
Standby Mode to Optimize Inductor Current Ripple and Efficiency
to Reverse DIMM Insertion
Incorporates Synchronous PWM Buck Controllers for VDDQ and
Integrated Power FETs with VTT Regulator Source/Sink up to 2.0 A
All External Power MOSFETs are N−Channel
Adjustable VDDQ and VMCH by External Dividers
VTT Tracks at Half the Reference Voltage
Fixed Switching Frequency of 250 kHz for VDDQ and VMCH
Doubled Switching Frequency of 500 kHz for VDDQ Controller in
Soft−Start Protection for all Controllers
Undervoltage Monitor of Supply Voltages
Overcurrent Protections for DDQ and VTT Regulators
Fully Complies with ACPI Power Sequencing Specifications
Short Circuit Protection Prevents Damage to Power Supply Due
Thermal Shutdown
5x6 QFN−20 Package
Pb−Free Package is Available*
DDR I and DDR II Memory and MCH Power Supply
Semiconductor Components Industries, LLC, 2005
1
DDQ_REF
†For information on tape and reel specifications,
NCP5210MNR2
NCP5210MNR2G
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
FBDDQ
FB1P5
COMP
FBVTT
PGND
VDDQ
AGND
Device
VTT
SS
1
NOTE: Pin 21 is the thermal pad
on the bottom of the device.
ORDERING INFORMATION
NCP5210 = Specific Device Code
A
WL
YY
WW
PIN CONNECTIONS
http://onsemi.com
CASE 505AB
20
MN SUFFIX
QFN−20
(Pb−Free)
Package
QFN−20
QFN−20
= Assembly Location
= Wafer Lot
= Year
= Work Week
Publication Order Number:
1
2500 Tape & Reel
2500 Tape & Reel
AWLYYWW
MARKING
DIAGRAM
NCP5210
Shipping
NCP5210/D
SW_DDQ
BG_DDQ
TG_DDQ
BOOT
COMP_1P5
GND_1P5
5VDUAL
BUF_Cut
TG_1P5
BG_1P5

Related parts for NCP5210MNR2G

NCP5210MNR2G Summary of contents

Page 1

... NOTE: Pin 21 is the thermal pad on the bottom of the device. ORDERING INFORMATION Device Package NCP5210MNR2 QFN−20 NCP5210MNR2G QFN−20 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. ...

Page 2

BUF_Cut BUF_Cut CSS VTT 1.25 V, VTT 2 Apk COUT2 FBVTT AGND DDQ_REF VDDQ CZM1 CZM2 COMP_1P5 CPM1 R5 RZM2 RZM1 FB_1P5 5VDUAL R6 TG_1P5 M3 VMCH L 1 BG_1P5 COUT3 M4 GND_1P5 NCP5210 SS BOOT 5VDUAL ...

Page 3

VREF VOLTAGE and CURRENT _VREFGD REFERENCE BUF_CUT VCC _BOOTGD BOOT_ R10 UVLO VREF R11 5VDUAL 5VDUAL_ R12 UVLO R13 _5VDLGD VREF OSC S0 CSS S3 1805 Phase Shift S0 VTT Regulation Control AGND NCP5210 THERMAL SHUTDOWN TSD S0 CONTROL S3 ...

Page 4

PIN DESCRIPTION Pin Symbol 1 COMP VDDQ error amplifier compensation node. 2 FBDDQ DDQ regulator feedback pin Soft−start pin of DDQ and MCH. 4 PGND Power ground. 5 VTT VTT regulator output. 6 VDDQ Power input for VTT ...

Page 5

ELECTRICAL CHARACTERISTICS (5VDUAL = 5 V, BOOT = 12 V, 5VATX = 5 V, DDQ_REF = 2 COUT1 = 3770 mF, COUT2 = 470 mF, COUT3 = NA, CSS = 33 nF 2.166 kW ...

Page 6

ELECTRICAL CHARACTERISTICS (5VDUAL = 5 V, BOOT = 12 V, 5VATX = 5 V, DDQ_REF = 2 COUT1 = 3770 mF, COUT2 = 470 mF, COUT3 = NA, CSS = 33 nF 2.166 kW ...

Page 7

TYPICAL OPERATING CHARACTERISTICS 1.196 1.194 1.192 1.19 1.188 1.186 1.184 1.182 AMBIENT TEMPERATURE ( C) A Figure 3. VFBQ Feedback Voltage vs. Ambient Temperature 0.81 0.805 0.8 0.795 0.79 0.785 ...

Page 8

TYPICAL OPERATING WAVEFORMS Channel 2: VDDQ Output Voltage, 1.0 V/div Channel 3: VTT Output Voltage, 1.0 V/div Channel 4: V1P5 Output Voltage, 1.0 V/div Time Base: 5.0 ms/div Figure 9. Power−Up Sequence Channel 1: Current Sourced out of VTT, 2.0 ...

Page 9

TYPICAL OPERATING WAVEFORMS Channel 1: Current Sourced into of VDDQ, 10 A/div Channel 2: VDDQ Output Voltage, AC−Coupled, 100 mV/div Channel 3: VTT Output Voltage, AC−Coupled, 100 mV/div Channel 4: V1P5 Output Voltage, AC−Coupled, 100 mV/div Time Base: 1.0 ms/div ...

Page 10

General The NCP5210 3−In−1 PWM Dual Buck Linear DDR Power Controller contains two high efficiency PWM controllers and an integrated two−quadrant linear regulator. The VDDQ supply is produced by a PWM switching controller with two external N−Ch FETs. The VTT ...

Page 11

For enhanced efficiency, an active synchronous switch is used to eliminate the conduction loss contributed by the forward voltage of a diode or Schottky diode rectifier. Adaptive non−overlap timing control of the complementary gate drive output signals is provided to ...

Page 12

BUF_CUT SS pin DDQ−S0 VTT MCH State 5VSTBY or 5VSTB is the Ultimate Chip Enable. This supply has first to ensure gates ...

Page 13

BUF_CUT = 0 AND _BOOTGD = 1 NOTE: All possible state transitions are shown. All unspecified inputs do not cause any state change. Figure 17. State Transitions Diagram of NCP5210 NCP5210 S5 BUF_CUT = 0 AND (_BOOTGD = 0) S0 ...

Page 14

100 C10 R7 6 VDDQ 1 COMP Vref = 1. FBDDQ PGND VTT VDDQ 6 ...

Page 15

Application Circuit Figure 18 shows the typical application circuit for NCP5210. The NCP5210 is specifically designed as a total power solution for the MCH and DDR memory system. This diagram contains NCP5210 for driving four external N−Ch FETs to form ...

Page 16

... V 1 ECJ1VB1E333K http://onsemi.com 16 Manufacturer ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor − − Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic − − − − − − − − − − − − ...

Page 17

QFN−20, DUAL−SIDED, 6x5 PIN 1 LOCATION TOP VIEW 0. SIDE VIEW (A3 20X 20X 20X ...

Page 18

... Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com NCP5210 N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 18 ON Semiconductor Website: http://onsemi ...

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