NCP5210 ON Semiconductor, NCP5210 Datasheet
NCP5210
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NCP5210 Summary of contents
Page 1
... PWM Dual Buck and Linear DDR Power Controller The NCP5210, 3−in−1 PWM Dual Buck and Linear DDR Power Controller complete power solution for MCH and DDR memory. This IC combines the efficiency of PWM controllers for the VDDQ supply and the MCH core supply voltage with the simplicity of linear regulator for the VTT termination voltage ...
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... CZM2 COMP_1P5 CPM1 R5 RZM2 RZM1 FB_1P5 5VDUAL R6 TG_1P5 M3 VMCH L 1 BG_1P5 COUT3 M4 GND_1P5 NCP5210 SS BOOT 5VDUAL TG_DDQ NCP5210 SW_DDQ BG_DDQ PGND COMP CZ1 FBDDQ VDDQ Figure 1. Application Diagram http://onsemi.com Zener 5VDUAL M1 VDDQ 2 COUT1 M2 CZ2 R1 RZ1 ...
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... BOOT_ R10 UVLO VREF R11 5VDUAL 5VDUAL_ R12 UVLO R13 _5VDLGD VREF OSC S0 CSS S3 1805 Phase Shift S0 VTT Regulation Control AGND NCP5210 THERMAL SHUTDOWN TSD S0 CONTROL S3 LOGIC VOCP ILIM + + − VDDQ and V1P5 PGND PWM V CC LOGIC PGND VREF ...
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... This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) "2.0 kV per JEDEC standard: JESD22–A114. Machine Model (MM) "200 V per JEDEC standard: JESD22–A115. 2. Latchup Current Maximum Rating: "150 mA per JEDEC standard: JESD78. NCP5210 Description Symbol ...
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... Minimum Duty Cycle Maximum Duty Cycle Soft−Start Pin Current for DDQ DDQ ERROR AMPLIFIER DC Gain Gain−Bandwidth Product Slew Rate 3. Guaranteed by design, not tested in production. NCP5210 Symbol Test Conditions V5VDUAL VBOOT I5VDL_S0 BUF_Cut = LOW, BOOT = 12 V, TG_1P5 and BG_1P5 Open ...
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... Control Loop in Regulation Feedback Input Current Oscillator Frequency Oscillator Ramp Amplitude Minimum Duty Cycle Maximum Duty Cycle Soft−Start Pin Current for V1P5 regulator 4. Guaranteed by design, not tested in production. NCP5210 Symbol Test Conditions dVTTS0 2.0 A (Sink Current) OUT –2.0 A (Source Current) ...
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... Figure 5. VFB1P5 Feedback Voltage vs. Ambient Temperature −5 −5.5 −6 −6.5 −7 −7.5 −8 −8 AMBIENT TEMPERATURE ( C) A Figure 7. VTT Source Current Load Regulation vs. Ambient Temperature NCP5210 550 500 450 400 350 300 250 200 Figure 4. Oscillation Frequency in S0/S3 30 29 ...
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... Channel 3: VTT Output Voltage, AC−Coupled, 50 mV/div Channel 4: V1P5 Output Voltage, AC−Coupled, 100 mV/div Time Base: 200 ms/div Figure 11. VTT Source Current Transient, 0A−2A−0A NCP5210 Channel 1: BUF_CUT Pin Voltage, 5.0 V/div Channel 2: VDDQ Output Voltage, AC−Coupled, 20 mV/div Channel 3: VTT Output Voltage, AC−Coupled, 100 mV/div Channel 4: V1P5 Output Voltage, AC− ...
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... Channel 1: Current Sourced into of VDDQ, 2.0 A/div Channel 2: VDDQ Output Voltage, AC−Coupled, 20 mV/div Time Base: 1.0 ms/div Figure 15. S3 Mode without 12VATX, 0A−2A−0A NCP5210 Channel 1: Current Sourced into of V1P5, 10 A/div Channel 2: VDDQ Output Voltage, AC−Coupled, 100 mV/div Channel 3: VTT Output Voltage, AC−Coupled, 50 mV/div Channel 4: V1P5 Output Voltage, AC− ...
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... General The NCP5210 3−In−1 PWM Dual Buck Linear DDR Power Controller contains two high efficiency PWM controllers and an integrated two−quadrant linear regulator. The VDDQ supply is produced by a PWM switching controller with two external N−Ch FETs. The VTT termination voltage is an integrated linear regulator with sourcing and sinking current capability which tracks at 1/2 VDDQ ...
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... VDDQ with the internal gate drive power derived from 5VDUAL. While VTT output is connecting to the FBVTT pin directly, VTT voltage is designed to automatically track NCP5210 at the half of DDQ_REF. This regulator is stable with any value of output capacitor greater than 470 mF, and is insensitive to ESR ranging from 1−mW to 400 mW. ...
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... V and 5 V ramp back to regulation. 12. BUF_CUT goes LOW. 13 UVLO = L and BUF_CUT = L. MCH ramps with SS pin, timing is 0 14. S0 Mode. 15. Prepare S5 Mode − BUF_CUT = L, and 12VUVLO = H or 5VUVLO = H. 16. DDQ, VTT, and MCH Turned OFF. 17. S5 Mode. Figure 16. NCP5210 Timing Diagram NCP5210 Switching Frequency Doubles 7 8 ...
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... BUF_CUT = 0 AND _BOOTGD = 1 NOTE: All possible state transitions are shown. All unspecified inputs do not cause any state change. Figure 17. State Transitions Diagram of NCP5210 NCP5210 S5 BUF_CUT = 0 AND (_BOOTGD = 0) S0 BUF_CUT = 0 AND BUF_CUT = 1 _BOOTGD = 1 http://onsemi.com 13 S3 ...
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... DPAK BUF_CUT TG_1P5 12 BG_1P5 11 +C21 GND_1P5 100 mF C11 220 nF DPAK R9 1 4.7 DPAK R10 1 4.7 COMP_1P5 Vref = 800 mV AGND to PGND SGND Figure 18. NCP5210 Typical Application Circuit Filtered D1 BAT54HT1 D2 BAT54HT1 4 ZENER Q1 MMSZ13T1 L2 85N02R 1 VDDQ 4 85N02R AGND to +C7 3 2200 mF PGND ...
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... MOSFETs. PCB Layout Consideration With careful PCB layout the NCP5210 can supply more current very important to use wide traces or large copper shades to carry current from the input node through the MOSFET switches, inductor, and to the output filters and load ...
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... Table 2. Bill of Material of NCP5210 Application Circuit Ref Design Description Q1, Q2 Power MOSFET N−Channel Q3, Q4 Power MOSFET N−Channel D1, D2 Rectifier Schottky Diode U1 Controller Zener Zener Diode L1 Toroidal Choke L2, L3 Toroidal Choke C2, C3 Aluminum Electrolytic Capacitor C5 Aluminum Electrolytic Capacitor C21 Aluminum Electrolytic Capacitor ...
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... E2 K 20X 20X 0.10 C 0.05 C BOTTOM VIEW NCP5210 PACKAGE DIMENSIONS MN SUFFIX CASE 505AB−01 ISSUE A NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994 DIMENSIONS IN MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINALS AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS ...
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... USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 18 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NCP5210/D ...