ISL6263CRZ Intersil, ISL6263CRZ Datasheet - Page 10

• Manufacturer Part Number: ISL6263CRZ
• Description: IC VREG CORE 5BIT 1PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6263CRZ

• Applications: Converter, Intel IMVP-6
• Voltage - Input: 5 ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 0.41 ~ 1.29 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Theory of Operation
The R
The heart of the ISL6263 is Intersil’s Robust-Ripple-
Regulator (R
of fixed frequency PWM control, and variable frequency
hysteretic control that will simultaneously affect the PWM
switching frequency and PWM duty cycle in response to
input voltage and output load transients.
The term “Ripple” in the name “Robust-Ripple-Regulator”
refers to the synthesized voltage-ripple signal V
appears across the internal ripple-capacitor C
signal is a representation of the output inductor ripple
current. Transconductance amplifiers measuring the input
voltage of the converter and the output set-point voltage
V
A voltage window signal V
COMP pins by sourcing a current proportional to g
through a parallel network consisting of resistor R
capacitor C
along with similar companion signals are converted into
PWM pulses.
The PWM frequency is proportional to the difference in
amplitude between V
large-amplitude, low noise synthesized signals allows the
ISL6263 to achieve lower output ripple and lower phase jitter
than either conventional hysteretic or fixed frequency PWM
controllers. Unlike conventional hysteretic converters, the
ISL6263 has an error amplifier that allows the controller to
maintain tight voltage regulation accuracy throughout the
VID range from 0.41200V to 1.28750V.
SOFT
TABLE 2. VID TABLE FOR INTEL IMVP-6+ V
, together produce the voltage-ripple signal V
3
Modulator
FSET.
CORE (Continued)
3
VID4
) Technology™. The R
1
1
1
1
1
1
1
1
1
1
1
1
1
1
The synthesized voltage-ripple signal V
VID3
W
0
0
0
0
0
0
1
1
1
1
1
1
1
1
and V
W
VID2
10
is created across the VW and
0
0
1
1
1
1
0
0
0
0
1
1
1
1
COMP
VID1
. Operating on these
3
1
1
0
0
1
1
0
0
1
1
0
0
1
1
modulator is a hybrid
VID0
CCGFX
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R.
R
The V
FSET
that
0.82400V
0.79825V
0.77250V
0.74675V
0.72100V
0.69525V
0.66950V
0.64375V
0.61800V
0.59225V
0.56650V
0.54075V
0.51500V
0.41200V
m
V
R
CCGFX
V
(V)
.
soft
R
and
R
ISL6263
Power-On Reset
The ISL6263 is disabled until the voltage at the VDD pin has
increased above the rising VDD power-on reset (POR)
V
disabled when the voltage at the VDD pin decreases below
the falling POR V
Start-Up Timing
Figure 4 shows the ISL6263 start-up timing. Once VDD has
ramped above V
pulling the VR_ON pin voltage above the input-high
threshold V
capacitor C
set-point as it is charged by the soft-start current source I
The V
V
counts 6 switching cycles, then changes the open-drain
output of the PGOOD pin to high impedance. During
soft-start, the regulator always operates in continuous
conduction mode (CCM).
Static Regulation
The V
by the VID inputs per Table 2. A true differential amplifier
connected to the VSEN and RTN pins implements processor
socket Kelvin sensing for precise core voltage regulation at
the GPU voltage sense points.
As the load current increases from zero, the V
voltage will droop from the VID set-point by an amount
proportional to the IMVP-6+ load line. The ISL6263 can
accommodate DCR current sensing or discrete resistor
current sensing. The DCR current sensing uses the intrinsic
series resistance of the output inductor as shown in the
application circuit of Figure 2. The discrete resistor current
sensing uses a shunt connected in series with the output
inductor as shown in the application circuit of Figure 3. In
both cases the signal is fed to the non-inverting input of the
DROOP amplifier at the VSUM pin, where it is measured
differentially with respect to the output voltage of the
converter at the VO pin and amplified. The voltage at the
DD_THR
SOFT
V
SOFT
CCGFX
CCGFX
voltage ramp to within 10% of the VID set-point then
/V
PGOOD
threshold voltage. The controller will become
VR_ON
CCGFX
VR_ONH
SOFT
FIGURE 4. ISL6263 START-UP TIMING
output voltage will be regulated to the value set
output voltage of the converter follows the
DD_THR
DD_THF
begins slewing to the designated VID
~100µs
. Approximately 100µs later, the soft-start
, the controller can be enabled by
threshold voltage.
6 SWITCHING CYCLES
90%
CCGFX
June 10, 2010
output
FN9213.2
SS
.