L6714 STMicroelectronics, L6714 Datasheet - Page 65

• Manufacturer Part Number: L6714
• Description: IC CTRLR 4PH W/DRIVERS 64-TQFP
• Manufacturer: STMicroelectronics

Specifications of L6714

• Applications: Controller, Intel VR10, VR11, AMD CPU
• Voltage - Input: 12V
• Number Of Outputs: 4
• Voltage - Output: 0.3 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP Exposed Pad, 64-eTQFP, 64-HTQFP, 64-VQFP
• Mounting Style: SMD/SMT
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

L6714
24.2
Small signal components and connections
These are small signal components and connections to critical nodes of the application as
well as bypass capacitors for the device supply
capacitor (VCC, VCCDRx and Bootstrap capacitor) close to the device and refer sensible
components such as frequency set-up resistor R
resistor R
single point to avoid that drops due to the high current delivered causes errors in the device
behavior.
VSEN pin filtered vs. SGND helps in reducing noise injection into device and OUTEN pin
filtered vs. SGND helps in reducing false trip due to coupled noise: take care in routing
driving net for this pin in order to minimize coupled noise.
Figure 26. Power connections and related connections layout (same for all phases).
Remote Buffer Connection must be routed as parallel nets from the FBG/FBR pins to the
load in order to avoid the pick-up of any common mode noise. Connecting these pins in
points far from the load will cause a non-optimum load regulation, increasing output
tolerance.
Locate current reading components close to the device. The PCB traces connecting the
reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up
of any common mode noise. It's also important to avoid any offset in the measurement and,
to get a better precision, to connect the traces as close as possible to the sensing elements.
Symmetrical layout is also suggested. Small filtering capacitor can be added, near the
controller, between V
higher layout flexibility.
UGATEx
PHASEx
LGATEx
PGNDx
Warning:
OVP
to SGND. Star grounding is suggested: connect SGND to PGND plane in a
Boot Capacitor Extra Charge. Systems that do not use
Schottky diodes might show big negative spikes on the
phase pin. This spike can be limited as well as the positive
spike but has an additional consequence: it causes the
bootstrap capacitor to be over-charged. This extra-charge
can cause, in the worst case condition of maximum input
voltage and during particular transients, that boot-to-phase
voltage overcomes the abs. max. ratings also causing device
failures. It is then suggested in this cases to limit this extra-
charge by adding a small resistor in series to the boot diode
(one resistor can be enough for all the three diodes if placed
upstream the diode anode,
standard and low-capacitive diodes.
OUT
V
C
IN
IN
and SGND, on the CSx- line when reading across inductor to allow
L
LOAD
PHASEx
BOOTx
SGND
(See Figure
VCC
OSC
See Figure
To limit C
, offset resistor R
BOOT
Extra-Charge
+Vcc
26). Locate the bypass
26) and by using
OFFSET
V
C
Layout guidelines
IN
IN
L
and OVP
65/70
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