L6714 STMicroelectronics, L6714 Datasheet - Page 10

• Manufacturer Part Number: L6714
• Description: IC CTRLR 4PH W/DRIVERS 64-TQFP
• Manufacturer: STMicroelectronics

Specifications of L6714

• Applications: Controller, Intel VR10, VR11, AMD CPU
• Voltage - Input: 12V
• Number Of Outputs: 4
• Voltage - Output: 0.3 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP Exposed Pad, 64-eTQFP, 64-HTQFP, 64-VQFP
• Mounting Style: SMD/SMT
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin settings
10/70
Table 1.
40 to
N°
33
34
35
36
37
38
39
45
VID_SEL
VID5 to
FAULT
VID7/
OSC/
DVID
VID6
VID0
OVP
FBR
FBG
Pin
Pin functions
Over Voltage Programming Pin. Internally pulled up by 12.5µA(typ) to 5V.
Set free to use built-in protection thresholds as reported into
Connect to SGND through a R
OVP threshold to a fixed voltage according to the R
See “Over voltage and programmable OVP” Section
Intel Mode.
It allows selecting between VR10 (short to SGND,
(floating,Table 6
the device” Section
AMD Mode. Not Applicable. Needs to be shorted to SGND.
Remote Buffer Non Inverting Input.
Connect to the positive side of the load to perform remote sense.
See “Layout guidelines” Section
Remote Buffer Inverting Input.
Connect to the negative side of the load to perform remote sense.
See “Layout guidelines” Section
Oscillator Pin.
It allows programming the switching frequency F
equivalent switching frequency at the load side results in being multiplied by the
phase number N.
Frequency is programmed according to the resistor connected from the pin vs.
SGND or VCC with a gain of 6kHz/µA (see relevant section for details). Leaving
the pin floating programs a switching frequency of 150kHz per phase.
The pin is forced high (5V) to signal an OVP FAULT: to recover from this
condition, cycle VCC or the OUTEN pin.
VID7 - Intel Mode. See VID5 to VID0 Section.
DVID - AMD Mode. DVID Output.
CMOS output pulled high when the controller is performing a D-VID transition
(with 32 clock cycle delay after the transition has finished).
transitions” Section
Intel Mode. See VID5 to VID0 Section.
AMD Mode. Not Applicable. Need to be shorted to SGND.
Intel Mode. Voltage IDentification Pins (also applies to VID6, VID7).
Internally pulled up by 25µA to 5V, connect to SGND to program a '0' or leave
floating to program a '1'.
They allow programming output voltage as specified in
according to VID_SEL status. OVP and UVP protection comes as a
consequence of the programmed code
AMD Mode. Voltage IDentification Pins.
Internally pulled down by 12.5µA, leave floating to program a '0' while pull up to
more than 1.4V to program a '1'.
They allow programming the output voltage as specified in
(VID7 doesn’t care). OVP and UVP protection comes as a consequence of the
programmed code
Note. VID6 not used, need to be shorted to SGND.
) DACs ,internally pulled up by 12.5 A (typ.)..
(See Table
for details.
Section for details.
10).
OVP
for proper layout of this connection.
for proper layout of this connection.
resistor and filter with 100pF (max) to set the
Function
(See Table
See “Oscillator” Section
SW
Table
10).
OVP
of each channel: the
Section for details.
Table 6
resistor.
7) or VR11
See “Dynamic VID
Table 9 on page 21
Table
See “Configuring
and
for details.
10.
Table 7
L6714