LTC3734EUH#TRPBF Linear Technology, LTC3734EUH#TRPBF Datasheet - Page 17

• Manufacturer Part Number: LTC3734EUH#TRPBF
• Description: IC CTRLR DC/DC 1PH HI EFF 32QFN
• Manufacturer: Linear Technology

Specifications of LTC3734EUH#TRPBF

• Applications: Controller, Intel Mobile CPU
• Voltage - Input: 4 ~ 30 V
• Number Of Outputs: 1
• Voltage - Output: 0.7 ~ 1.71 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
Output Voltage Set in Deep Sleep and Deeper Sleep
States (Refer to the Functional Diagram)
The output voltage can be offset by the STP_CPUB signal.
When STP_CPUB becomes low, the output voltage will be
a certain percentage lower than that set by the VID bits in
Table 1. This state is defined to be the deep sleep state.
Referring to the Functional Diagram, we can calculate the
STP_CPUB offset to be:
By using different R4 resistors, STP_CPUB offset can be
programmed.
The output voltage could also be set by external resistors
R4 and R6 when DPRSLPVR input is high. This state is
defined to be the deeper sleep state. The output voltage
is set to V
Where R6||R4 is the parallel combination of R4 and R6.
(=(INTERNAL PG)
AND (MCH_PG))
STP
V
COMPOSITE PG
COMPARATOR)
POWER GOOD
INTERNAL PG
DPRSLPVR
(OUTPUT OF
INTERNAL
MCH_PG
VID BITS
RUN/SS
% –
V
OUT
MD
=
DPRSLPVR
Figure 4. Start-Up Timing Diagram
R
=
3
R
0 6
+
INVALID
3
1.5V
.
U
R
, regardless of the VID setting:
V
4
•
•
V
(
100
R
BOOT
90% V
R R
U
2
6 4
•
BOOT
%
t
TIME
(
BOOT
R
3
)
+
•
(
R R
R
W
1
6 4
V
VALID
VID
+
R
2
)
)
3734 F04
U
By using different value R6 resistors, V
programmed.
(The digital input threshold voltage is 1.8V for STP_CPUB,
DPRSLPVR and MCH_PG inputs.)
Power Good Masking
The PGOOD output monitors V
within ±10% of the set point, PGOOD is pulled low with an
internal MOSFET. When V
window, PGOOD is of high impedance. PGOOD should be
pulled up by an external resistor.
During VID changes, deep sleep and deeper sleep transi-
tions, the output voltage can initially be out of the ±10%
window of the newly set regulation point. To avoid nui-
sance indications from PGOOD, a timer masks PGOOD for
110μs. If output is still out of regulation after this blanking
time, PGOOD goes low. Any overvoltage or undervoltage
condition is also masked for 110μs before it is reported by
PGOOD.
The masking circuitry also adaptively tracks VID and state
changes. If a new change in VID or state happens before
the 110μs masking timer expires, the timer resets and
starts a fresh count of 110μs. This prevents the system
from rebooting under frequent output voltage transitions.
Refer to Figure 5 for the PGOOD timing diagram.
During start up, PGOOD is actively pulled low until the
RUN/SS pin voltage reaches its arming voltage, which is
COMPARATOR)
POWER GOOD
INTERNAL PG
(OUTPUT OF
INTERNAL
MASKING
VID BITS
PGOOD
PGOOD
V
OUT
Figure 5. PGOOD Timing Diagram
110μs
OUT
TIME
is within the regulation
OUT
. When V
110μs
DPRSLPVR
LTC3734
3734 F05
OUT
17
can be
is not
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