LTC3734EUH Linear Technology, LTC3734EUH Datasheet - Page 21

• Manufacturer Part Number: LTC3734EUH
• Description: IC CTRLR DC/DC 1PH HI EFF 32QFN
• Manufacturer: Linear Technology

Specifications of LTC3734EUH

• Applications: Controller, Intel Mobile CPU
• Voltage - Input: 4 ~ 30 V
• Number Of Outputs: 1
• Voltage - Output: 0.7 ~ 1.71 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
Efficiency varies as the inverse square of V
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance of
loss terms in the switching regulator system!
2) Transition losses apply only to the topside MOSFET(s),
and are significant only when operating at high input
voltages (typically 12V or greater). Transition losses can
be estimated from:
3) PV
driver current results from switching the gate capacitance
of the power MOSFETs. Each time a MOSFET gate is
switched from low to high to low again, a packet of charge
dQ moves from PV
current out of PV
control circuit current. In continuous mode, I
(Q
topside and bottom side MOSFETs and f is the switching
frequency.
4) The input capacitor has the difficult job of filtering the
large RMS input current to the regulator. It must have a
very low ESR to minimize the AC I
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
Other losses, including C
conduction loss during dead time, inductor core loss and
internal control circuitry supply current generally account
for less than 2% additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, V
amount equal to ΔI
T
Transition Loss V
+ Q
CC
B
drives both top and bottom MOSFETs. The MOSFET
)f, where Q
CC
LOAD
CC
U
=
that is typically much larger than the
T
⎛
⎜
⎝
and Q
to ground. The resulting dQ/dt is a
IN
V
(ESR), where ESR is the effective
DR
2
U
OUT
•
–
B
I
OUT
are the gate charges of the
2
V
1
ESR loss, Schottky diode
TH MIN
(
• •
f C
2
W
R loss and sufficient
)
RSS
+
OUT
V
TH MIN
•
shifts by an
R
(
1
OUT
DR
GATECHG
U
)
•
for the
⎞
⎟
⎠
=
series resistance of C
discharge C
forces the regulator to adapt to the current change and
return V
time V
ringing, which would indicate a stability problem. The
availability of the I
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time, and settling at this test point truly reflects the
closed loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at the pin. The I
shown in the Figure 1 circuit will provide an adequate
starting point for most applications.
The I
loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon first because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of <1μs will
produce output voltage and I
give a sense of the overall loop stability without breaking
the feedback loop. The initial output voltage step resulting
from the step change in output current may not be within
the bandwidth of the feedback loop, so this signal cannot
be used to determine phase margin. This is why it is
better to look at the I
loop and is the filtered and compensated control loop
response. The gain of the loop will be increased by
increasing R
increased by decreasing C
same factor that C
be kept the same, thereby keeping the phase the same in
the most critical frequency range of the feedback loop.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
TH
OUT
OUT
series R
can be monitored for excessive overshoot or
OUT
to its steady-state value. During this recovery
C
and the bandwidth of the loop will be
generating the feedback error signal that
C
-C
C
TH
is decreased, the zero frequency will
TH
C
OUT
pin not only allows optimization of
filter sets the dominant pole-zero
pin signal which is in the feedback
. ΔI
C
LOAD
. If R
TH
TH
pin waveforms that will
also begins to charge or
C
external components
is increased by the
LTC3734
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3734f