LTC3734EUH Linear Technology, LTC3734EUH Datasheet - Page 10

• Manufacturer Part Number: LTC3734EUH
• Description: IC CTRLR DC/DC 1PH HI EFF 32QFN
• Manufacturer: Linear Technology

Specifications of LTC3734EUH

• Applications: Controller, Intel Mobile CPU
• Voltage - Input: 4 ~ 30 V
• Number Of Outputs: 1
• Voltage - Output: 0.7 ~ 1.71 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC3734
OPERATIO
Main Control Loop
The LTC3734 uses a constant frequency, current mode
step-down architecture. During normal operation, the top
MOSFET is turned on when the clock sets the RS latch, and
turned off when the main current comparator, I
the RS latch. The peak inductor current at which I
the RS latch is controlled by the voltage on the I
which is the output of error amplifier EA. The V
receives the voltage feedback signal, which is compared to
the internal reference voltage by the EA. When the load
current increases, it causes a slight decrease in EA invert-
ing input node relative to the 0.6V reference, which in turn
causes the I
tor current matches the new load current. After the top
MOSFET has turned off, the bottom MOSFET is turned on
until either the inductor current starts to reverse, as
indicated by current comparator I
next cycle.
The top MOSFET driver is biased from a floating bootstrap
capacitor C
cycle through an external diode when the top MOSFET
turns off. As V
loop may enter dropout and attempt to turn on the top
MOSFET continuously. The dropout detector detects this
and forces the top MOSFET off for about 500ns every sixth
cycle to allow C
The main control loop is shut down by pulling the RUN/
SS pin low. Releasing RUN/SS allows an internal 1.5μA
current source to charge soft-start capacitor C
C
the internal I
its maximum value. As C
internal I
full-current operation.
Frequency Programming
The switching frequency of the LTC3734 is determined by
the DC voltage at the FREQSET pin. A DC voltage ranging
from 0V to 2.4V moves the internal oscillator frequency
from 210kHz to 550kHz.
10
SS
reaches 1.5V, the main control loop is enabled with
TH
B
voltage is gradually released allowing normal,
TH
, which normally is recharged during each off
TH
IN
voltage to increase until the average induc-
voltage clamped at approximately 30% of
B
decreases to a voltage close to V
to recharge.
U
(Refer to Functional Diagram)
SS
continues to charge, the
2
, or the beginning of the
SS
1
OUT
1
, resets
. When
TH
FB
resets
, the
pin,
pin
Low Current Operation (PSIB)
The PSIB pin selects between two modes of operation.
When PSIB is above 0.6V, the controller operates in full
synchronous switching mode. Bottom driver (BG) is kept
on once it is turned on until the oscillator sets the RS latch.
The inductor current can therefore go from output back to
input power supply and could potentially boost the input
supply to dangerous voltage levels—BEWARE! This mode
of operation is also of lower efficiency and much current
can circulate between input and output. However, this
mode provides constant switching frequency.
When PSIB is below 0.6V, the bottom driver (BG) is
turned off if the inductor current starts to reverse. This
mode of operation prevents current going from output
back to input and eliminates the conduction power loss
related to circulating current. The circuit may skip switch-
ing cycles at very light load conditions.
Output Voltage at Start-Up and at Deeper Sleep State
Under normal conditions, the output voltage of the regu-
lator is commanded by six VID bits, except at start-up and
at deeper sleep state. At start-up, the RUN/SS capacitor
starts to charge up and its voltage limits the inrush current
from the input power source. This linearly rising current
limit provides a controlled output voltage rise. During
start-up, the VID command is ignored and the output set
point is determined by the value of the resistor connected
to the RBOOT pin. The VID bits continue to be ignored for
15 switching cycles after the completion of the following
two conditions: 1) output voltage has risen up and has
regulated 2) MCH_PG signal has asserted. After 15 switch-
ing cycles, output voltage is fully commanded by VID bits.
In deeper sleep state, the VID command is also ignored
and the output set point is determined by the parallel value
of the resistors at the RDPRSLP pin and RDPSLP pin.
3734f