MC34716EP Freescale Semiconductor, MC34716EP Datasheet - Page 21

• Manufacturer Part Number: MC34716EP
• Description: IC CONVERTER DDR 26QFN
• Manufacturer: Freescale Semiconductor

Specifications of MC34716EP

• Applications: Converter, DDR
• Voltage - Input: 3 ~ 6 V
• Number Of Outputs: 2
• Voltage - Output: 0.7 ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 26-QFN
• Output Voltage: 0.7 V to 3.6 V
• Output Current: 5 A
• Input Voltage: 3 V to 6 V
• Switching Frequency: 1 MHz
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SELECTING INDUCTOR
Channels. The equation is the following:
it is necessary to locate the LC poles at different frequencies
in order to ensure that the input impedance of the second
converter is always higher than the output impedance of the
first converter, and thus, ensure system stability. This can be
achieved by selecting different values for L1 and L2 slightly
higher than the calculated value.
SELECTING THE OUTPUT FILTER CAPACITOR
most important and not the actual Farad value: the physical
size, the ESR of the capacitor, and the voltage rating.
following formula:
transient response.)
Analog Integrated Circuit Device Data
Freescale Semiconductor
r _
Δ
Rds
L
T
D
Inductor calculation process is the same for both
If channel 1 will be serving as power supply for channel 2,
For the output capacitor, the following considerations are
Calculate the minimum output capacitor using the
Transient Response percentage:
TR_%
(Use a recommended value of 2 to 4% to assure a good
Maximum Transient Voltage:
TR_V_dip = V
Maximum Current Step:
I
=
'
OUT
Δ
MAX
w
(
Iout
D
on
'
=
=
MAX
_ )
1
0
_
Co
4 .
−
∗
ls
step
T
Vin
*
=
OUT
∗
I
OUT
V
(
I
=
_
V
out
OUT
*TR_%
out
max
(
TR
Vin
+
*
_
dt
I
_
out
V
Maximum Off Time Percentage
Switching Period
Drain – to – Source
Resistance of FET
Winding Resistance of Inductor
Output Current Ripple
min
_
_
( *
I
dip
_
Rds
−
Fsw
rise
Δ
Vout
I
(
out
*
on
L
* )
_ )
D
ls
_
+
max
r
_
w
))
allowed ESR.
ers and may present a hidden danger to the ultimate supply
stability. Poor quality capacitors have widely disparate ESR
value, which can make the closed loop response inconsis-
tent.
BOOTSTRAP CAPACITOR
voltage for the high side MOSFET. This N-Channel MOSFET
needs a voltage difference between its gate and source to be
able to turn on. The high side MOSFET source is the SW
node, so it is not at ground and it is floating and shifting in
voltage. We cannot just apply a voltage directly to the gate of
the high side that is referenced to ground. We need a voltage
referenced to the SW node. This is why the bootstrap
capacitor is needed. This capacitor charges during the high
side off time. Since the low side will be on during that time,
the SW node and the bottom of the bootstrap capacitor will be
connected to ground, and the top of the capacitor will be
connected to a voltage source. The capacitor will charge up
to that voltage source (for example 5.0 V). Now when the low
side MOSFET switches off and the high side MOSFET
switches on, the SW nodes rise to V
boot pin will be V
V
capacitor is a good value for this bootstrap element.
TYPE III COMPENSATION NETWORK
regulation output voltages. A high DC gain is required to
accomplish this, but with high gain comes the possibility of
instability. The purpose of adding compensation to the
internal error amplifier is to counteract some of the gains and
phases contained in the control-to-output transfer function
that could jeopardized the stability of the power supply. The
Type III compensation network used for 34716 is comprised
of two poles (one integrator and one high frequency, to
cancel the zero generated from the ESR of the output
capacitor) and two zeros to cancel the two poles generated
from the LC filter as shown in
CAP
Inductor Current Rise Time:
The following formula will be helpful to find the maximum
The bootstrap capacitor is needed to supply the gate
Power supplies are desired to offer accurate and tight
The effects of the ESR is often neglected by the design-
across it and it will be able to stay enhanced. A 0.1 μf
ESR
dt
CAP
_
max
I
+ V
_
=
rise
Δ
V
IN
OUT
. The gate of the high side will have
V
OUT
=
1 (
Figure
Δ
*
−
I
T
OUT
Fsw
D
IN
*
TYPICAL APPLICATIONS
, and the voltage on the
12.
min)
I
_
OUT
*
step
L
34716
21