ISL6244CR Intersil, ISL6244CR Datasheet - Page 13

• Manufacturer Part Number: ISL6244CR
• Description: IC CTRLR PWM 2-4-PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6244CR

• Pwm Type: Voltage/Current Mode
• Number Of Outputs: 4
• Frequency - Max: 4MHz
• Duty Cycle: 75%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 4MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The integrating compensation network shown in Figure 17
assures that the steady-state error in the output voltage is
limited to the error in the reference voltage (output of the
DAC) plus offset errors in the OFS current source, remote-
sense and error amplifiers. Intersil specifies the guaranteed
tolerance of the ISL6244 to include all variations in current
sources, amplifiers and the reference so that the output
voltage remains within the specified system tolerance of
±
any external component tolerances.
1
%. The 1% does not include the VID offset tolerance or
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TABLE 1. VOLTAGE IDENTIFICATION CODES
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
13
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Shutdown
1.550
1.525
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.300
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
DAC
ISL6244
FEED-FORWARD RAMP COMPENSATION
The ISL6244 features a V
modulator gain. The V
network from the battery voltage, as illustrated in Figure 18.
The V
oscillator relative to the battery voltage. By feeding the
battery voltage forward, the pulse width modulation gain,
G
The ramp modulator gain is then set by the ratio of the
maximum duty cycle, d
programmed by the resistor network on the V
typical applications, select R
R
in a constant pulse width modulator gain of 7.5 over the
entire range of battery voltage (see note below).
NOTE: the V
.
LOAD-LINE REGULATION
Microprocessor load current demands change from near no-
load to full load often during operation. The resulting sizable
transient current slew rate causes an output voltage spike
since the converter is not able to respond fast enough to the
rapidly changing current demands. The magnitude of the
spike is dictated by the ESR and ESL of the output
capacitors selected. In order to drive the cost of the output
capacitor solution down, one commonly accepted approach
is active voltage positioning. By adding a well controlled
output impedance, the output voltage can effectively be level
shifted in a direction which works against the voltage spike.
The average current of all the active channels, I
out IOUT, see Figure 17. IOUT is connected to FB through a
load-line regulation resistor, R
across R
creating an output voltage droop with a steady-state value
defined as
V
G
ADJ2
FIGURE 18. BATTERY VOLTAGE FEED-FORWARD
DROOP
mod
mod
, is independent of battery voltage, see Equation 5.
FF
=
for a 1/10 attenuation of the battery voltage, resulting
PWM
---------------------------------------------------------------------------------------- -
------------------------------------------------- V
R
FB
voltage sets the peak-to-peak voltage of the ramp
=
ADJ1
FF
I
is proportional to the output current, effectively
+
AVG
-
R
d
V
ISL6244 INTERNAL CIRCUITRY
COMPENSATION
ADJ2
SAWTOOTH
MAX V BATTERY
voltage must be bounded between 0.5V and 2.5V.
COMP
+
SIGNAL
R
R
ADJ2
FB
⋅
FF
MAX
⋅
voltage is set by a resistor divider
FF
GENERATOR
BATTERY
SAWTOOTH
, to the amount of attenuation
ADJ1
pin for setting the pulse width
FB
. The resulting voltage drop
to be 9 times the value of
=
0.75x10
V
PWM1
FF
FF
=
December 28, 2004
AVG
7.5
pin. For
V
BATTERY
, flows
FN9106.3
(EQ. 5)
(EQ. 6)
R
R
ADJ1
ADJ2