ISL6244CR Intersil, ISL6244CR Datasheet - Page 11

• Manufacturer Part Number: ISL6244CR
• Description: IC CTRLR PWM 2-4-PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6244CR

• Pwm Type: Voltage/Current Mode
• Number Of Outputs: 4
• Frequency - Max: 4MHz
• Duty Cycle: 75%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 4MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PWM Operation
The timing of each converter leg is set by the number of
active channels. The default channel setting for the ISL6244
is four. One switching cycle is defined as the time between
PWM1 pulse termination signals. The pulse termination
signal is an internally generated clock signal which triggers
the falling edge of PWM1. The cycle time of the pulse
termination signal is the inverse of the switching frequency
set by the resistor between the FS pin and ground. Each
cycle begins when the clock signal commands the channel-1
PWM output to go low. The PWM1 transition signals the
channel-1 MOSFET driver to turn off the channel-1 upper
MOSFET and turn on the channel-1 synchronous MOSFET.
In the default channel configuration, the PWM2 pulse
terminates 1/4 of a cycle after PWM1. The PWM 3 output
follows another 1/4 of a cycle after PWM2. PWM4 terminates
another 1/4 of a cycle after PWM3.
If PWM3 is connected to VCC, then two channel operation is
selected and the PWM2 pulse terminates 1/2 of a cycle later.
Connecting PWM4 to VCC selects three channel operation and
the pulse-termination times are spaced in 1/3 cycle increments.
Once a PWM signal transitions low, it is held low for a
minimum of 1/4 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
is driven by the position of the error amplifier output signal,
V
sawtooth ramp as illustrated in Figure 1. When the modified
V
transitions high. The MOSFET driver detects the change in
state of the PWM signal and turns off the synchronous
MOSFET and turns on the upper MOSFET. The PWM signal
will remain high until the pulse termination signal marks the
beginning of the next cycle by triggering the PWM signal low.
Current Sensing
During the forced off time following a PWM transition low, the
controller senses channel load current by sampling the
voltage across the lower MOSFET r
ground-referenced amplifier, internal to the ISL6244,
connects to the PHASE node through a resistor, R
voltage across R
across the R
conducting. The resulting current into the ISEN pin is
proportional to the channel current, I
then sampled and held after sufficient settling time every
switching cycle. The sampled current, I
channel-current balance, load-line regulation and
overcurrent protection. From Figure 15, the following
equation for I
where I
I
n
COMP
COMP
=
I
L
, minus the current correction signal relative to the
L
r
----------------------
voltage crosses the sawtooth ramp, the PWM output
DS ON
R
is the channel current.
ISEN
(
DS(ON)
n
)
is derived
ISEN
of the lower MOSFET while it is
is equivalent to the voltage drop
11
DS(ON)
L
. The ISEN current is
n
, is used for
, see Figure 15. A
ISEN
(EQ. 3)
. The
ISL6244
If R
sense resistor in series with the lower MOSFET source can
serve as a sense element. The circuitry shown in Figure 15
represents channel n of an N-channel converter. This
circuitry is repeated for each channel in the converter, but
may not be active depending upon the status of the PWM3
and PWM4 pins as described in the previous section.
Channel-Current Balance
The sampled current, I
gauge both overall load current and the relative channel
current carried in each leg of the converter. The individual
sample currents are summed and divided by the number of
active channels. The resulting average current, I
provides a measure of the total load current demand on the
converter and the appropriate level of channel current. Using
Figures 15 and 16, the average current is defined as:
I
I
where N is the number of active channels and I
total load current.
The average current is then subtracted from the individual
channel sample currents. The resulting error current, I
then filtered before it adjusts V
signal is compared to a sawtooth ramp signal and produces
a pulse width which corrects for any imbalance and drives
the error current toward zero. Figure 16 illustrates Intersil’s
patented current-balance method as implemented on
channel-1 of a multi-phase converter.
AVG
AVG
SAMPLE
FIGURE 15. INTERNAL AND EXTERNAL CURRENT-SENSING
HOLD
DS(ON)
ISL6244 INTERNAL CIRCUIT
&
I
n
=
=
I
----------------------------------
I
------------ -
1
OUT
I SEN
N
+
sensing is not desired, an independent current-
I
2
N
r
----------------------
CIRCUITRY
+
=
DS ON
R
…I
ISEN
I
L
(
r DS ON
------------------------- -
N
+
-
R ISEN
)
(
n
, from each active channel is used to
)
ISEN(n)
EXTERNAL CIRCUIT
COMP
CHANNEL N
LOWER MOSFET
R
. The modified V
ISEN
V
IN
+
CHANNEL N
UPPER MOSFET
-
I L r DS ON
December 28, 2004
OUT
AVG
I
L
is the
,
(
COMP
FN9106.3
ER
(EQ. 4)
)
, is