ISL8120IRZ-T Intersil, ISL8120IRZ-T Datasheet - Page 17

• Manufacturer Part Number: ISL8120IRZ-T
• Description: IC CTRLR PWM 2/NPHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL8120IRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1.5MHz
• Duty Cycle: 90%
• Voltage - Supply: 3 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Pin Description
GND (Pin 33, Signal and Power Ground Pad)
All voltage levels are referenced to this pad.This pad
provides a return path for the low-side MOSFET drives and
internal power circuitries as well as all analog signals.
Connect this pad to the circuit ground using the shortest
possible path (more than 5 to 6 via to the internal ground
plane, placed on the soldering pad are recommended).
VIN (Pin 16, Internal Linear Regulator Input)
This pin should be tied directly to the input rail when using
the internal linear regulator. It provides power to the internal
linear drive circuitry. When used with an external 5V supply,
this pin should be tied directly to PVCC. The internal linear
device is protected against reverse bias generated by the
remaining charge of the decoupling capacitor at PVCC when
losing the input rail.
VCC (Pin 26, Analog Circuit Bias)
This pin provides power for the analog circuitry. A RC filter is
recommended between the connection of this pin to a 3V to
5.6V bias (typically PVCC). R is suggested to be a 5Ω
resistor. And in 3.3V applications, the R could be shorted to
allow the low end input in concerns of the VCC falling
threshold. The VCC decoupling cap C is strongly
recommended to be as large as 10µF ceramic capacitor.
This pin can be powered either by the internal linear
regulator or by an external voltage source.
BOOT1, 2 (Pins 25, 17)
This pin provides the bootstrap bias for the high-side driver.
Internal bootstrap diodes connected to the PVCC pin provide
the necessary bootstrap charge. Its typical operational
voltage range is 2.5V to 5.6V.
UGATE1, 2 (Pin 24, 8)
These pins provide the drive for the high-side devices and
should be connected to the MOSFETs’ gates.
PHASE1, 2 (Pins 23,19)
Connect these pins to the source of the high-side MOSFETs
and the drain of the low-side MOSFETs. These pins
represent the return path for the high-side gate drives.
PVCC (Pin 21, Driver Bias Voltage)
This pin is the output of the internal series linear regulator. It
provides the bias for both low-side and high-side drives. Its
operational voltage range is 3V to 5.6V. The decoupling
ceramic capacitor in the PVCC pin is 10µF.
LGATE1, 2 (Pins 22, 20)
These pins provide the drive for the low-side devices and
should be connected to the MOSFETs’ gates.
FSYNC (Pin 5)
The oscillator switching frequency is adjusted by placing a
resistor (R
FS
) from this pin to GND. The internal oscillator
17
ISL8120IRZEC
will lock to an external frequency source if this pin is
connected to a switching square pulse waveform, typically
the CLKOUT input signal from another ISL8120IRZEC or an
external clock. The internal oscillator synchronizes with the
leading edge of the input signal.
EN/FF1, 2 (Pins 4, 6)
These are triple function pins. The input voltages to these
pins are compared with a precision 0.8V reference and
enable their digital soft-starts. By pulling this pin to voltage
lower than the threshold, the corresponding channel can be
disabled independently. Connecting these pins to input bus
through a voltage resistor divider can monitor the input
voltage. The undervoltage lockout and its hysteresis levels
can be programmed by setting the values of the resistor
dividers. The voltages on these pins are also fed into
controller to be used to adjust the amplitude of each
individual sawtooth independently.
Furthermore, during fault (such as overvoltage, overcurrent,
and over-temperature) conditions, these pins (EN/FF_) are
used to communicate the information to other cascaded ICs
by pulling low.
PGOOD (Pin 8)
Provides an open drain Power-Good signal when both
channels are within 9% of nominal output regulation point
with 4% hysteresis (13%/9%) and soft-start is complete.
PGOOD monitors the outputs (VMON1/2) of the internal
differential amplifiers.
ISEN1A, 2A (Pins 27, 15)
These pins are the positive inputs of the current sensing
amplifier. Together with ISEN1B,2B, these pins provide
r
ISEN1B, 2B (Pins 28, 14)
These pins are the negative inputs of the current sensing
amplifier. Together with the ISEN1A, 2A pins they provide
r
“Typical Application III (2-Phase Operation with r
Sensing and Voltage Trimming)” on page 7 for r
sensing set up and “Typical Application V (4 Phase
Operation with DCR Sensing)” on page 9 for DCR sensing
set-up.
ISET (Pin 2)
This pin sources an 15µA offset current plus the average
current of both channels in multiphase mode or only
Channel 1’s current in independent mode. The voltage
(V
average current level of the local active channel(s). V
compared with a 1V threshold for average overcurrent
protections. For full-scale current, R
1V/120µA = 8.33kΩ. Typically 10kΩ is used for R
DS(ON)
DS(ON)
ISET
) set by an external resistor (R
, DCR, or precision resistor current sensing.
, DCR, or precision resistor current sensing. Refer to
ISET
ISET
should be
) represents the
DS(ON)
DS(ON)
SET
April 21, 2009
.
ISET
FN6763.1
is