ISL6306IRZ Intersil, ISL6306IRZ Datasheet - Page 27

• Manufacturer Part Number: ISL6306IRZ
• Description: IC CTRLR PWM 4-PHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6306IRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 66.7%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

required. When load line function is not needed, IDROOP
pin can used to obtain the load current information: with one
resistor from IDROOP pin to GND, the voltage at IDROOP
pin will be proportional to the load current. The resistor from
IDROOP to GND should be chosen to ensure that the
voltage at IDROOP pin is less than 2V under the maximum
load current.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and
example board layouts for all common microprocessor
applications.
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board; whether through-hole components are permitted; and
the total board space available for power-supply circuitry.
Generally speaking, the most economical solutions are
those in which each phase handles between 15A and 20A.
All surface-mount designs will tend toward the lower end of
this current range. If through-hole MOSFETs and inductors
can be used, higher per-phase currents are possible. In
cases where board space is the limiting constraint, current
can be pushed as high as 40A per phase, but these designs
require heat sinks and forced air to cool the MOSFETs,
inductors and heat-dissipating surfaces.
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching
frequency; the capability of the MOSFETs to dissipate heat;
and the availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
MOSFET is due to current conducted through the channel
resistance (r
continuous output current; I
current (see Equation 1); d is the duty cycle (V
L is the per-channel inductance.
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
P
LOW 1
,
=
r
DS ON
DS(ON)
(
)
). In Equation 23, I
⎛
⎜
⎝
I
----- -
N
M
⎞
⎟
⎠
2
(
1 d
PP
–
27
)
is the peak-to-peak inductor
+
I
--------------------------------- -
L P-P
,
2
12
M
(
1 d
is the maximum
–
)
OUT
/V
IN
(EQ. 23)
); and
ISL6306
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I
frequency, f
the beginning and the end of the lower-MOSFET conduction
interval respectively.
Thus the total maximum power dissipated in each lower
MOSFET is approximated by the summation of P
P
UPPER MOSFET POWER CALCULATION
In addition to r
MOSFET losses are due to currents conducted across the
input voltage (V
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times; the lower-MOSFET body-diode reverse-
recovery charge (Q
conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 25,
the required time for this commutation is t
approximated associated power loss is P
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t
approximate power loss is P
A third component involves the lower MOSFET’s reverse-
recovery charge (Q
commutated to the upper MOSFET before the lower-
MOSFET’s body diode can draw all of Q
through the upper MOSFET across V
dissipated as a result is P
Finally, the resistive part of the upper MOSFET’s is given in
Equation 28 as P
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
P
P
P
P
LOW,2
LOW 2
UP 1 ,
UP 2 ,
UP 3 ,
,
≈
≈
=
.
V
V
=
V
IN
IN
IN
V
⎛
⎝
S
⎛
⎜
⎝
D ON
I
----- -
Q
N
I
----- -
; and the length of dead times, t
N
M
M
(
rr
DS(ON)
+
–
IN
f
S
I
---------- -
I
---------- -
UP,4
)
P-P
P-P
) during switching. Since a substantially
2
2
f
S
rr
rr
⎞ t
⎠
⎞ t
⎟
⎠
) and the upper MOSFET r
). Since the inductor current has fully
⎛
⎝
.
⎛
⎜
⎝
⎛
⎜
⎝
losses, a large portion of the upper-
I
----- -
N
----
----
M
2
2
2
1
⎞
⎟
⎠
⎞
⎟
⎠
+
M
UP,3
f
f
S
S
I
---------- -
, V
P-P
2
UP,2
2
D(ON)
⎞ t
⎠
and is approximately
. In Equation 26, the
.
d1
+
; the switching
IN
⎛
⎜
⎝
I
----- -
N
M
. The power
rr
UP,1
–
1
, it is conducted
I
---------- -
and the
P-P
2
d1
.
⎞
⎟
⎠
and t
DS(ON)
t
d2
LOW,1
May 5, 2008
d2
(EQ. 24)
(EQ. 25)
(EQ. 26)
(EQ. 27)
FN9226.1
, at
and