ISL6540ACRZ Intersil, ISL6540ACRZ Datasheet - Page 19

• Manufacturer Part Number: ISL6540ACRZ
• Description: IC CTLR PWM BUCK 1PHASE 28-QFN
• Manufacturer: Intersil

Specifications of ISL6540ACRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 100%
• Voltage - Supply: 2.97 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 2MHz
• Number Of Pwm Outputs: 1
• On/off Pin: No
• Adjustable Output: Yes
• Topology: Buck
• Switching Freq: 250 TO 2000kHz
• Operating Supply Voltage (max): 5.5V
• Output Current: 4A
• Output Voltage: 0.6 to 20V
• Synchronous Pin: No
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: QFN EP
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

It is recommended that a mathematical model is used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
compensation (G
As before when tieing VFF to VIN terms in the previous
equations can be simplified as shown in Equation 17:
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 10 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual modulator gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the previous guidelines should yield
a compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain, G
log-log graph of Figure 10 by adding the modulator gain,
G
dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
G
D
------------------------------ -
F
F
Z1
Z2
MOD
MOD
MAX
G
G
V
FB
CL
R
C
OSC
=
=
3
3
f ( )
f ( )
f ( )
⋅
(in dB), to the feedback compensation gain, G
------------------------------ -
2π R
-------------------------------------------------
2π
V
=
=
IN
=
=
--------------------- -
------------------------------------------------ -
2π R
=
F
----------- - 1
⋅
⋅
F
(
SW
LC
1
R
D
------------------------------ -
--------------------------------------------------- - ⋅
s f ( ) R
------------------------------------------------------------------------------------------------------------------------ -
(
G
=
R
2
1
⋅
1
1
MAX
MOD
1
⋅
-------------------------- -
0.16 V
+
V
–
+
1
+
C
3
1 V
OSC
⋅
s f ( ) R
1
R
s f ( ) R
⋅
⋅
FB
1
0.7 F
⋅
f ( ) G
3
1
⋅
V
) C
⋅
⋅
IN
) and closed-loop response (G
⋅
IN
⋅
(
⋅
⋅
IN
C
1
3
P2
3
⋅
2
1
SW
+
FB
⋅
---------------------------------------------------------------------------------------------------------- -
1
=
⋅
+
C
s f ( )
C
+
against the capabilities of the error
f ( )
C
3
6.25
1
s f ( )
)
2
F
F
⋅
)
⋅
19
P1
P2
⎛
⎜
⎝
(
1
R
⋅
(
1
+
CL
=
=
ESR
+
where s f ( )
s f ( ) R
1
, is constructed on the
-------------------------------------------- -
2π R
------------------------------ -
2π R
R
+
3
s f ( ) ESR C
⋅
⋅
⋅
+
) C
⋅
DCR
1
,
MOD
2
2
3
⋅
⋅
3
⋅
⋅
1
⎛
⎜
⎝
-------------------- -
C
C
C
-------------------- -
C
C
) C
3
1
1
), feedback
=
1
⋅
1
+
⋅
+
⋅
C
2π f j
⋅
C
C
C
+
2
2
2
2
s
⋅ ⋅
CL
⎞
⎟
⎠
2
⎞
⎟
⎠
f ( ) L C
(EQ. 15)
(EQ. 16)
(EQ. 17)
(EQ. 18)
):
FB
⋅
(in
⋅
ISL6540A
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the switching frequency, F
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1.0µF
ceramic capacitors in the 1206 surface-mount package.
Follow on specifications have only increased the number
and quality of required ceramic decoupling capacitors.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor's ESR value is related to
the case size with lower ESR available in larger case sizes.
FIGURE 10. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
0
LOG
20
log
⎛
⎝
R2
------- -
R1
⎞
⎠
F
Z1
F
F
LC
Z2
SW
F
F
CE
P1
.
F
0
F
20
P2
log
G
CL
D
---------------------------------- -
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
G
MAX V
V
MOD
OSC
FREQUENCY
⋅
IN
October 7, 2008
G
FB
FN6288.5