ISL6540ACRZ Intersil, ISL6540ACRZ Datasheet - Page 11

• Manufacturer Part Number: ISL6540ACRZ
• Description: IC CTLR PWM BUCK 1PHASE 28-QFN
• Manufacturer: Intersil

Specifications of ISL6540ACRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 100%
• Voltage - Supply: 2.97 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 2MHz
• Number Of Pwm Outputs: 1
• On/off Pin: No
• Adjustable Output: Yes
• Topology: Buck
• Switching Freq: 250 TO 2000kHz
• Operating Supply Voltage (max): 5.5V
• Output Current: 4A
• Output Voltage: 0.6 to 20V
• Synchronous Pin: No
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: QFN EP
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OV/UV/PGOOD comparators. The VMON pin should be
connected to the FB pin by a standard feedback network. In
the event of the remote sense buffer is disabled, the VMON
pin should be connected to VOUT by a resistor divider along
with FB’s compensation network. An RC filter should be
used if VMON is to be connected directly to FB instead of to
VOUT through a separate resistor divider network.
GND (Bottom Side Pad, Analog Ground)
Signal ground for the IC. All voltage levels are measured
with respect to this pin. This pin should not be left floating.
Functional Description
Initialization
The ISL6540A automatically initializes upon receipt of power
without requiring any special sequencing of the input
supplies. The Power-On Reset (POR) function continually
monitors the input supply voltages (PVCC, VFF, VCC) and
the voltage at the EN pin. Assuming the EN pin is pulled to
above ~0.50V, the POR function initiates soft-start operation
after all input supplies exceed their POR thresholds.
With all input supplies above their POR thresholds, driving
the EN pin above 0.50V initiates a soft-start cycle. In addition
to normal TTL logic, the enable pin can be used as a voltage
monitor with programmable hysteresis through the use of the
internal 10µA sink current and an external resistor divider.
This feature is especially designed for applications that have
PVCC POR
VCC POR
VFF POR
V
R
FIGURE 1. SOFT-START INITIALIZATION LOGIC
R
HIGH = ABOVE POR; LOW = BELOW POR
EN POR
EN_FTH
DOWN
UP
=
R
FIGURE 2. ENABLE POR CIRCUIT
V
------------------------- - 1kΩ
DOWN
I
EN_HYS
=
EN_HYS
R
=
1kΩ
R
EN
(
------------------------------------------------------------------
UP
VIN
R
V
V
UP
EN_RTH
EN_FTH
+
EN
–
1kΩ
–
–
AND
) V
11
V
V
V
•
EN_REF
EN_HYS
EN_REF
EN_REF
I
EN_HYS
SOFT-START
=10µA
SYS_ENABLE
ISL6540A
input rails greater than a 3.3V and require a specific input rail
POR and Hysteresis levels for better undervoltage
protection. Consider for a 12V application choosing
R
rising threshold (V
(V
should be taken to prevent the voltage at the EN pin from
exceeding VCC when using the programmable UVLO
functionality.
Soft-Start
The POR function activates the internal 37µA OTA which
begins charging the external capacitor (C
target voltage of VCC. The ISL6540A’s soft-start logic continues
to charge the SS pin until the voltage on COMP exceeds the
bottom of the oscillator ramp, at which point, the driver outputs
are enabled with the low side MOSFET first being held low for
200ns to provide for charging of the bootstrap capacitor. Once
the driver outputs are enabled, the OTA’s target voltage is then
changed to the margined (if margining is being used) reference
voltage (V
accordingly. This method reduces start-up surge currents due
to a pre-charged output by inhibiting regulator switching until
the control loop enters its linear region. By ramping the positive
input of the error amplifier to VCC and then to V
even possible to mitigate surge currents from outputs that are
pre-charged above the set output voltage. As the SS pin
connects directly to the non-inverting input of the error amplifier,
noise on this pin should be kept to a minimum through careful
routing and part placement. To prevent noise injection into the
error amplifier the SS capacitor should be located within 150
mils of the SS and GND pins. Soft-start is declared done when
the drivers have been enabled and the SS pin is within ±3mV of
V
T
REF_MARG
UP
PG_DLY
EN_FTH
FIGURE 3. UNDERVOLTAGE-OVERVOLTAGE WINDOW
= 97.6kΩ and R
REF_MARG
) to ~9V, for ~1V of hysteresis (V
=
UV
.
C
PG_DLY
GOOD
EN_RTH
), and the SS pin is ramped up or down
DOWN
⋅
1.49V
--------------- -
21μA
) to ~10V and the falling threshold
VMON
= 5.76kΩ there by setting the
OV
SS
GOOD
) on the SS pin to a
EN_HYS
REF_MARG
UV
V
REF_MARG
October 7, 2008
). Care
+15%
+9%
-9%
-15%
FN6288.5
(EQ. 1)
, it is