ISL6540ACRZ Intersil, ISL6540ACRZ Datasheet - Page 18

• Manufacturer Part Number: ISL6540ACRZ
• Description: IC CTLR PWM BUCK 1PHASE 28-QFN
• Manufacturer: Intersil

Specifications of ISL6540ACRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 100%
• Voltage - Supply: 2.97 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 2MHz
• Number Of Pwm Outputs: 1
• On/off Pin: No
• Adjustable Output: Yes
• Topology: Buck
• Switching Freq: 250 TO 2000kHz
• Operating Supply Voltage (max): 5.5V
• Output Current: 4A
• Output Voltage: 0.6 to 20V
• Synchronous Pin: No
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: QFN EP
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 9 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, when using an internal
differential remote sense amplifier. The output voltage
(V
The error amplifier output (COMP pin voltage) is compared
with the oscillator (OSC) triangle wave to provide a
pulse-width modulated wave with an amplitude of V
PHASE node. The PWM wave is smoothed by the output
filter (L and C). The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of V
DC gain, given by D
output filter, with a double pole break frequency at F
zero at F
represent the total output capacitance and its equivalent
series resistance.
The compensation network consists of the error amplifier
(internal to the ISL6540A) and the external R
C
provide a closed loop transfer function with high 0dB crossing
F
LC
3
OUT
FIGURE 9. VOLTAGE-MODE BUCK CONVERTER
components. The goal of the compensation network is to
CIRCUIT
=
PWM
) is regulated to the reference voltage, VREF, level.
---------------------------
2π
CE
⋅
COMP
1
. For the purpose of this analysis C and ESR
L C
OUT
COMPENSATION DESIGN
⋅
HALF-BRIDGE
OSCILLATOR
/V
V
OSC
E/A
DRIVE
COMP
MAX
R
ISL6540A
2
V
C
. This function is dominated by a
F
+
-
VREF
+
2
-
CE
IN
C
/V
18
1
=
OSC
-------------------------------- -
2π C ESR
FB
PHASE
UGATE
LGATE
VMON
VSEN-
VSEN+
EXTERNAL CIRCUIT
⋅
, and shaped by the
1
R
⋅
3
V
IN
R
C
1
SEN
1
C
L
3
thru R
DCR
R
V
ESR
OS
3
OUT
LC
IN
C
, C
R
(EQ. 10)
FB
at the
and a
1
thru
ISL6540A
frequency (F
phase margin (better than 45°). Phase margin is the
difference between the closed loop phase at F
The equations that follow relate the compensation network’s
poles, zeros and gain to the components (R
and C
locating the poles and zeros of the compensation network:
1. Select a value for R
2. Calculate C
3. Calculate C
4. Calculate R
value for R
setting the output voltage to be equal to the reference set
voltage as shown in Figure 7, the design procedure can
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 9), in order
to compensate for the attenuation introduced by the
resistor divider, the below obtained R
multiplied by a factor of (R
of the calculations remain unchanged, as long as the
compensated R
A small capacitor,
out noise, typically
time constant does not reduce the overall phase margin
of the design, typically this is 2x to 10x switching
frequency of the regulator. As the ISL6540A supports
100% duty cycle, d
uses feedforward compensation, as such V
to 0.16 multiplied by the voltage at the VFF pin. When
tieing VFF to V
at 0.1 to 0.75 of F
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
frequency (to maximize phase boost at F
such that F
times F
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F
helps reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
COMP pin and minimizing resultant duty cycle jitter.
C
C
R
R
1
2
2
2
3
) in Figures 7 and 9. Use the following guidelines for
=
=
=
=
---------------------------------------------- -
2π R
------------------------------------------------------- -
2π R
-------------------------------------------- -
d
0.16 R
----------------------------------
V
SW
MAX
0
OSC
⋅
⋅
; typically 0.1 to 0.3 of F
F
). F
⋅
P2
2
1
2
2
2
3
LC
⋅
such that F
⋅
⋅
for desired converter bandwidth (F
V
such that F
such that F
⋅
1
1
0.5 F
C
SW
is placed below F
C
R
IN
⋅
IN
1
F
1
1
2
⋅
⋅
0
, the Equation 12 simplifies to:
LC
⋅
⋅
represents the regulator’s switching
value is used.
F
F
F
C
LC
C
MAX
CE
0
LC
SEN
1
(to adjust, change the 0.5 factor to
SEN
(1kΩ to 10kΩ, typically). Calculate
–
Z1
P1
in Figure 9, can be added to filter
1
Z2
equals 1. The ISL6540A also
is chosen so the corresponding
OS
is placed at a fraction of the F
is placed at F
is placed at F
+R
SW
CE
FB
SW
/F
)/R
(typically, 0.5 to 1.0
LC
P2
) and adequate
2
OS
1
, the lower the F
lower in frequency
value needs be
LC
CE
, R
LC
. The remainder
0dB
).
. Calculate C
2
.
OSC
, R
October 7, 2008
and 180°.
3
0
, C
is equal
). If
(EQ. 12)
(EQ. 13)
(EQ. 14)
(EQ. 11)
FN6288.5
1
, C
LC
Z1
2
3
,
,