ADM1028ARQ ON Semiconductor, ADM1028ARQ Datasheet - Page 12

• Manufacturer Part Number: ADM1028ARQ
• Description: IC SENSOR TEMP/FAN CTRL 16QSOP
• Manufacturer: ON Semiconductor

Specifications of ADM1028ARQ

• Rohs Status: RoHS non-compliant
• Function: Fan Control, Temp Monitor
• Topology: ADC, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: 0°C ~ 100°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP

ADM1028
GENERAL-PURPOSE LOGIC INPUT (GPI)
Pin 2 is used as a general-purpose logic input with 12 V toler-
ance. The GPI input may be programmed to be active high or
active low by clearing or setting Bit 6 of the Configuration Reg-
ister. The default value is active high. Bit 4 of the Interrupt Status
register follows the state (or inverted state) of GPI and will gen-
erate an interrupt when it is set to 1, like any other input to the
Interrupt Status Register. However, the GPI bit is not latched
in the Status Register and always reflects the current state (or
inverted state) of the GPI input. If it is 1, it will not be cleared
by reading the Status Register.
POWER-ON RESET
When the ADM1028 is powered up, it will initiate a power-on
reset sequence when the supply voltage V
the power-on reset threshold, with registers being reset to their
power-on values. Normal operation will begin when the supply
voltage rises above the reset threshold. Registers whose power-
on values are not shown have power-on conditions that are
indeterminate (this includes the Value and Limit Registers). In
most applications, usually the first action after power-on would
be to write limits into the Limit Registers.
Power-on reset clears or initializes the following registers (the
initialized values are shown in Table III):
∑ Configuration Register
∑ Interrupt Status Register
∑ Interrupt Mask Register
∑ Analog Output Register
∑ Programmable Trip Point Registers
The ADM1028 can also be reset by taking AUXRST low as an
input. All registers will be reset to their default values and the
ADC will remain inactive as long as AUXRST is below the
reset threshold. Taking the RST pin low will cause the following
registers to be reset.
∑ Bit 3 of the Configuration Register (Programmable THERM
∑ DAC Output, Fan Speed
INITIALIZATION (SOFT RESET)
Soft reset performs a similar, but not identical, function to
power-on reset. It restores the power-on default values to the
Configuration Register, the Interrupt Status Register and the
Interrupt Mask Register. The Limit Registers remain unchanged.
It rearms the INT structure but not the THERM structure.
Soft reset is accomplished by setting Bit 4 of the Configuration
Register high. This bit automatically clears after being set.
Unlike clearing INT, where the temperature must fall back within
the set limits for three conversions before the INT function is
rearmed, the soft reset allows INT to be pulled low immediately
after the soft reset.
Limit Lock Bit)
CC3AUX
rises above
–12–
NAND TREE TEST
A NAND tree is provided in the ADM1028 for Automated Test
Equipment (ATE) board level connectivity testing. The device
is placed into NAND tree test mode by powering up with pin
FAN_SPD/NTEST_IN (Pin 8) held high. This pin is sampled
and its state at power-up is latched. If it is connected high, then
the NAND tree test mode is invoked. NAND tree test mode will
only be exited once the ADM1028 is powered down.
In NAND tree test mode, all digital inputs may be tested as
illustrated in Table II. THERMA/NTEST_OUT will become
the NAND tree output pin.
The structure of the NAND Tree is shown in Figure 10. To per-
form a NAND Tree test, all pins are initially driven low. The
test vectors set all inputs low then, one-by-one, toggles them
high (keeping them high). Exercising the test circuit with this
“walking one” pattern, starting with the input closest to the
output of the tree, cycling toward the farthest, causes the out-
put of the tree to toggle with each input change. Allow for a
typical propagation delay of 500 ns.
CONFIGURING THE INTERRUPT
On power-up, the Interrupt functionality of the device is disabled.
The Configuration Register (0x40) must be written to, in order
to enable the interrupt output. The INT_Enable bit (Bit 1) of
the Register should be set to 1.
RST
0
0
0
0
0
1
AUXRST
FAN_SPD/
NTEST_IN
SDA
RST
SCL
GPI
AUXRST
0
0
0
0
1
1
D
POWER-ON
LATCH
RESET
Figure 10. NAND Tree
Table II. Test Vectors
CLK
GPI
0
0
0
1
1
1
Q
ENABLE
SDA
0
0
1
1
1
1
SCL
0
1
1
1
1
1
THERMA
1
0
1
0
1
0
THERMA/
NTEST_OUT
REV. B