ADM1026JST ON Semiconductor, ADM1026JST Datasheet - Page 29

• Manufacturer Part Number: ADM1026JST
• Description: IC CNTRL SYS REF/EEPROM 48LQFP
• Manufacturer: ON Semiconductor

Specifications of ADM1026JST

• Rohs Status: RoHS non-compliant
• Function: Hardware Monitor
• Topology: ADC, Comparator, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: 0°C ~ 100°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFQFP

may be pulled low externally as an input. This causes the
PWM and DAC outputs to go to full scale until THERM is
returned high again. To disable THERM as an input, set Bit 0
of Configuration Register 3 (Reg. 07h). This configures
Pin 42 as GPIO16 and prevents a low on Pin 42 from driving
the fans at full speed.
Reset Input and Outputs
outputs, RESETMAIN and RESETSTBY. These operate as
follows.
RESETSTBY is asserted (pulled low) until 180 ms after
3.3 V STBY rises above the reset threshold.
powerup, RESETMAIN is asserted (pulled low) until
180 ms after 3.3 V MAIN rises above the reset threshold.
remains asserted until 180 ms after RESETSTBY is
negated. RESETMAIN can also function as a RESET input.
Pulling this pin low resets the registers, which are initialized
to their default values by a software reset. (See the Software
Reset Function section for register details).
ADM1026. In applications that do not require monitoring of
a 3.3 V STBY and 3.3 V MAIN supply, these two pins should
be connected together (3.3 V MAIN should not be left
floating).
driven, the 3.3 V STBY supply should power on before all
other voltages in the system.
THERM LIMIT - 55C
Note that the THERM pin is bidirectional, so THERM
The ADM1026 has two active low, power−on reset
RESETSTBY monitors 3.3 V STBY. At powerup,
RESETMAIN monitors 3.3 V MAIN. This means that at
If 3.3 V MAIN rises with or before DV
Note that the 3.3 V STBY pin supplies power to the
To ensure that the 3.3 V STBY pin does not become back
See Table 1 for more information about pin configuration.
Figure 53. Assertion of INT Due to THERM Event
THERM LIMIT
THERM
INT
TEMPERATURE
INT CLEARED BY STATUS REG 1 READ,
BIT 2 OF CONFIG. REG. 1 SET, OR ARA
CC
, RESETMAIN
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29
NAND Tree Tests
test equipment (ATE) board−level connectivity testing. This
allows the functionality of all digital inputs to be tested in a
simple manner and any pins that are nonfunctional or
shorted together to be identified. The structure of the NAND
tree is shown in Figure 55. The device is placed into NAND
tree test mode by powering up with Pin 25 held high. This
pin is sampled automatically after powerup, and if it is
connected high, then the NAND test mode is invoked.
ways.
A NAND tree is provided in the ADM1026 for automated
The NAND tree test may be carried out in one of two
RESETSTBY
3.3VMAIN
RESETMAIN
3.3VSTBY
FAN7
SDA
SCL
INT
1. Start with all inputs low and take them high in
2. Start with all inputs high and take them low in
CI
turn, starting with the input nearest to
NTEST_OUT (GPIO16/ THERM) and working
back up the tree to the input furthest from
NTESTOUT (INT). This should give the
characteristic output pattern shown in Figure 56,
with NTESTOUT toggling each time an input is
taken high.
turn, starting with the input furthest from
NTEST_OUT (INT) and working down the tree to
the input nearest to NTEST_OUT
(GPIO16/THERM). This should give a similar
output pattern to Figure 57.
Figure 54. Operation of Offset Outputs
~1.0 V
~1.0 V
Figure 55. NAND Tree
180ms
GPIO8
FAN0
FAN1
FAN2
FAN3
FAN4
FAN5
FAN6
POWER−ON RESET
180ms
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO9
NTESTOUT