MAX6683AUB+T Maxim Integrated Products, MAX6683AUB+T Datasheet - Page 9

• Manufacturer Part Number: MAX6683AUB+T
• Description: IC TEMP SENSOR MON 10-UMAX
• Manufacturer: Maxim Integrated Products

Specifications of MAX6683AUB+T

• Function: Temp Monitoring System (Sensor)
• Topology: ADC, Multiplexer, Register Bank
• Sensor Type: Internal
• Sensing Temperature: -40°C ~ 125°C
• Output Type: I²C™/SMBus™
• Output Alarm: Yes
• Output Fan: No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Full Temp Accuracy: +/- 3 C
• Digital Output - Bus Interface: Serial (2-Wire)
• Digital Output - Number Of Bits: 10 bit + Sign
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6. Interrupt Mask Register (Address 43h, Power-Up Default = 00h)
Table 7. Temperature Configuration Register (Address 4Bh, Power-Up Default = 00h)
An out-of-range voltage or temperature causes the
ALERT output signal to be asserted. However, if the
assertion is caused by an out-of-range temperature, the
ALERT output can operate in one of three different
modes: default, one-time interrupt, or comparator
mode. In the default and one-time interrupt modes, the
ALERT signal and Interrupt Status Register are cleared
by reading the Interrupt Status Register (Table 5). In
comparator mode, ALERT is only cleared when the fault
condition is removed. Reading the Interrupt Status
Register clears all but bit 4 of the Status Register if the
fault condition is not removed. Reading the Interrupt
Status Register with the fault condition removed clears
the entire register. Unless the fault is removed, ALERT
is reasserted after the next conversion cycle. The
ALERT output can also be masked by writing to the
appropriate bits in the Interrupt Mask Register (Table 6)
or by setting bit 1 of the Configuration Register (Table
4) to zero.
The interrupt does not halt conversions. New tempera-
ture and voltage data continue to be available over the
SMBus interface after ALERT is asserted. The three
temperature ALERT modes are shown in Figure 1 and
5, 6, 7
0, 1
2−7
BIT
BIT
0
1
2
3
4
Hot Temperature
Interrupt Select
Reserved
Reserved
NAME
NAME
Temp.
2.5V
1.8V
3.3V
_______________________________________________________________________________________
5V
READ/WRITE
READ/WRITE
ALERT Interrupts
System Monitor in a 10-Pin µMAX
R/W
R/W
R/W
R/W
R/W
R/W
—
—
Setting the bit to 1 disables the Interrupt Status Register bit (bit 0) and the
ALERT output for the 2.5V
Setting the bit to 1 disables the Interrupt Status Register bit (bit 1) and the
ALERT output for the 1.8V
Setting the bit to 1 disables the Interrupt Status Register bit (bit 2) and the
ALERT output for the 5V
Setting the bit to 1 disables the Interrupt Status Register bit (bit 3) and the
ALERT output for the V
Setting the bit to 1 disables the Interrupt Status Register bit (bit 4) and the
ALERT output for temperature.
Bit 1, bit 0 = 00: Default mode
Bit 1, bit 0 = 01: One-time interrupt mode
Bit 1, bit 0 = 10: Comparator mode
Bit 1, bit 0 = 11: Default mode
Temperature Sensor and
are selected through the Temperature Configuration
Register (Table 7). The ALERT output pin is open drain,
so the device can share a common interrupt line.
An interrupt is initiated when temperature exceeds
T
reading the Interrupt Status Register. An interrupt con-
tinues to be generated on subsequent measurements
until the temperature goes below T
An interrupt is initiated when temperature exceeds
T
reading the Interrupt Status Register. The next interrupt
is then initiated when temperature falls below the T
(address 3Ah).
An interrupt is initiated when temperature exceeds
T
ed low until the temperature goes below T
the Interrupt Status Register does not clear the ALERT
output or interrupt status bit in the register. The inter-
rupt continues to be generated on subsequent mea-
surements until the temperature falls below T
HOT
HOT
HOT
(address 39h). The ALERT output remains assert-
(address 39h). The interrupt is cleared only by
(address 39h). The interrupt is cleared only by
CC
IN
IN
IN
input.
input.
input.
input.
DESCRIPTION
DESCRIPTION
—
—
One-Time Interrupt Mode
HYST
Comparator Mode
(address 3Ah).
Default Mode
HOT
HOT
. Reading
.
HYST
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