W83791G Nuvoton Technology Corporation of America, W83791G Datasheet - Page 18

• Manufacturer Part Number: W83791G
• Description: IC MONITOR H/W 48-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83791G

• Function: Hardware Monitor
• Topology: ADC
• Sensor Type: External
• Sensing Temperature: External Sensor
• Output Type: I²C™
• Output Alarm: Yes
• Output Fan: Yes
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3
6.3.1
The W83791D/G is a derivative of Winbond's PowerSpeech
hardware trigger inputs, 17 Hardware Monitor event and 128 programmable software event trigger
inputs. If more than two events happen simultaneously, the priority set by the internal H/W is:
SLOTOCC# > EVNTRAP1 > EVNTRAP2 > EVNTRAP3 > EVNTRAP4 > EVNTRAP5 > TRIGREG
(Index 09h) 128 events > VIN0 > VIN1> others (VIN2 –VIN9, TEMP, FAN, case open). Software
trigger is able to accommodate 128 event triggers, with timeout register (index 08h) enabled in
advance for allowance of time on detecting devices. That is, once the system’s power is on, BIOS can
fill trigger event and speech voice will not be sent till the system fails owing to timeout. In addition, to
prevent events from taking place simultaneously.
6.3.2
W83791D/G provides 8 byte FIFO queue to store event trigger, for example, the first 8 event can be
served by speech and speech will clear FIFO queue after service. Coding of Speech program must
assign correct CPU_MODE event vector to issue correct speech voices correspondent to speech
trigger events. For example, CPU_MODE event vector =1 represents absence of CPU, then coding
speech with CPU is absent voice. When W83791D/G detects no CPU exists, it will send vector = 1 to
speech synthesizer and play this voice data. Following is the block diagram of the 8-Byte event trigger
queue.
(b) Serial bus read from a register
Speech Function
SCL
SDA
General Description
Event Trigger Queue
Repeat
start
by
Master
Start By
Master
0
0
0
0
1
CLK 1 HZ
Serial Bus Address Byte
1
0
Figure 2. Serial Bus Read from Internal Address Register
Timeout Register
Serial Bus Address Byte
8-bit Counter
(Index 08h)
Frame 3
0
1
8-Byte Event Trigger Queue
Trigger
Frame 1
1
1
1
0
Figure 3. Event trigger Queue
0
1
1
R/W
7
0
791D
R/W
0
Ack
7
by
8
- 12 -
791D
Ack
by
8
0
D7
Comparator
Timeout
0
D7
D6
Data Byte
Frame 4
D6
D5
Internal Index Register Byte
D5
TM
Publication Release Date: April 14, 2006
D4
Frame 2
synthesizers. There are up to 5
D4
D3
D3
D2
Enable Timeout
(Index 09h, b6~0)
(Index 0Ah, b6)
D2
Trigger Data
D1
TRIG_REG
Event
D1
W83791D/G
7
D0
7
D0
Master
8
Ack
by
791D
8
Ack
Stop by
Master
by
Revision 1.1