HIP6501ACB-T Intersil, HIP6501ACB-T Datasheet - Page 8

• Manufacturer Part Number: HIP6501ACB-T
• Description: IC PWM TRIPLE POWER CTRLR 16SOIC
• Manufacturer: Intersil

Specifications of HIP6501ACB-T

• Applications: Power Supply Controller
• Voltage - Supply: 5V, 12V
• Current - Supply: 20mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Input: -

3V3DLSB
5VDLSB
INTERNAL
3V3DLSB
5VDLSB
3V3DL
FIGURE 6. 3V
FIGURE 7. 3V
5VSB
DEVICE
5VDL
3V3DL
VSEN2
VSEN2
DLA
5VSB
5VDL
12V
DRV2
5VSB
DLA
S3
S5
12V
12V
S3
S5
S3
S5
FIGURE 8. 2.5/3.3V
EN3VDL = 0, EN5VDL = 1
EN3VDL = 0, EN5VDL = 0
DUAL
DUAL
AND 5V
AND 5V
MEM
DUAL
DUAL
8
TIMING DIAGRAM
TIMING DIAGRAM FOR
TIMING DIAGRAM FOR
HIP6501A
Soft-Start Circuit
Soft-Start into Sleep States (S3, S4/S5)
The 5VSB POR function initiates the soft-start sequence. An
internal 10µA current source charges an external capacitor
to 5V. The error amplifiers reference inputs are clamped to a
level proportional to the SS (Soft-Start) pin voltage. As the
SS pin voltage slews from about 1.25V to 2.5V, the input
clamp allows a rapid and controlled output voltage rise.
Figure 9 shows the soft-start sequence for the typical
application start-up in a sleep state with all output voltages
enabled. At time T0 5V
time T1, 5V
charge circuit quickly raises the SS capacitor voltage to
approximately 1V. At this point, the 10µA current source
continues the charging up to T2, where a voltage of 1.25V
(typically) is reached and an internal clamp limits further
charging. Clamping of the soft-start voltage (T2 to T3
interval) should only be noticed with capacitors smaller than
0.1µF; soft-start capacitors of 0.1µF and above should
present a soft-start ramp void of this plateau. At time T3,
3ms (typically) past the 5V
voltage selection is latched in and the charging of the soft-
start capacitor resumes, using the 10µA current source. At
this point, the error amplifiers’ reference inputs are starting
their transitions, causing the output voltages to ramp up
proportionally. The ramping continues until time T4 when all
the voltages reach the set value. At time T5, when the soft-
start capacitor value reaches approximately 2.8V, the under-
voltage monitoring circuits are activated and the soft-start
capacitor is quickly discharged down to the value attained at
time T2 (approximately 1.25V).
0V
0V
FIGURE 9. SOFT-START INTERVAL IN A SLEEP STATE (ALL
T0
T1 T2 T3
SB
VOLTAGES
(1V/DIV)
OUTPUTS ENABLED)
5VSB
OUTPUT
(1V/DIV)
surpasses POR level, and an internal fast
SB
(bias) is applied to the circuit. At
SB
T4
POR (T1), the memory output
T5
UV DETECT ENABLE
TIME
SOFT-START
(LOGIC LEVEL)
(1V/DIV)
V
V
V
OUT3
OUT1
OUT2
(5V
(3.3V
(2.5V
December 30, 2004
DUAL
DUAL
MEM
)
FN4749.6
)
)