MAX8792ETD+T Maxim Integrated Products, MAX8792ETD+T Datasheet - Page 26

• Manufacturer Part Number: MAX8792ETD+T
• Description: IC PWM CONTROLLER 14TDFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8792ETD+T

• Applications: PWM Controller
• Voltage - Input: 2 ~ 26 V
• Current - Supply: 700µA
• Operating Temperature: -40°C ~ 80°C
• Mounting Type: Surface Mount
• Package / Case: 14-TDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Single Quick-PWM Step-Down
Controller with Dynamic REFIN
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows trade-offs between V
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
where V
is the parasitic voltage drop in the charge path, and
t
absolute minimum input voltage is calculated with h = 1.
If the calculated V
minimum input voltage, then reduce the operating fre-
quency or add output capacitance to obtain an accept-
able V
calculate V
response.
Dropout Design Example:
V
f
t
No droop/load line (V
V
h = 1.5:
Calculating again with h = 1 gives the absolute limit of
dropout:
Therefore, V
very large output capacitance, and a practical input volt-
age with reasonable output capacitance would be 2.0V.
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching
power stage requires particular attention. If possible,
mount all the power components on the top side of the
board with their ground terminals flush against one
another. Follow these guidelines for good PCB layout:
1) Keep the high-current paths short, especially at the
26
OFF(MIN)
SW
OFF(MIN)
FB
DROPCHG
ground terminals. This is essential for stable, jitter-
free operation.
= 300kHz
= 1.5V
______________________________________________________________________________________
V
V
IN MIN
IN MIN
SAG
V
FB
(
(
IN MIN
is from the Electrical Characteristics table. The
= 350ns
(
. If operation near dropout is anticipated,
is the voltage-positioning droop, V
= 150mV (10A load)
)
IN
)
SAG
=
=
)
⎡
⎢
⎣
must be greater than 1.84V, even with
Applications Information
⎡
⎢
⎣
=
1 1 0 350
1 1 5 350
−
−
⎛
⎜
⎝
to be sure of adequate transient
IN(MIN)
( .
V
( .
1 5
1 5
FB
.
DROOP
.
1
V
V
×
−
×
−
−
−
V
(
PCB Layout Guidelines
DROOP
0
h t
0
is greater than the required
V
V
×
ns
= 0)
ns
+
+
OFF MIN SW
150
150
×
×
300
300
+
(
mV
mV
V
kHz
DROPCHG
kHz
)
f
)
)
⎤
⎥ =
⎦
⎤
⎥ =
⎦
)
SAG
1 84
1 96
.
.
DROPCHG
⎞
⎟
⎠
, output
V
V
2) Connect all analog grounds to a separate solid
3) Keep the power traces and load connections short.
4) Keep the high-current, gate-driver traces (DL, DH,
5) When trade-offs in trace lengths must be made, it is
6) Route high-speed switching nodes away from sen-
1) Place the power components first, with ground ter-
2) Mount the controller IC adjacent to the low-side
3) Group the gate-drive components (BST capacitors,
4) Make the DC-DC controller ground connections as
copper plane, which connects to the GND pin of
the Quick-PWM controller. This includes the V
bypass capacitor, REF bypass capacitors, REFIN
components, and feedback compensation/dividers.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance full-
load efficiency by 1% or more. Correctly routing PC
board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance causes
a measurable efficiency penalty.
LX, and BST) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
sitive analog areas (REF, REFIN, FB, ILIM).
minals adjacent (low-side MOSFET source, C
C
connections on the top layer with wide, copper-
filled areas.
MOSFET. The DL gate traces must be short and
wide (50 mils to 100 mils wide if the MOSFET is 1in
from the controller IC).
V
shown in the Standard Application Circuits . This
diagram can be viewed as having four separate
ground planes: input/output ground, where all the
high-power components go; the power ground
plane, where the PGND pin and V
capacitor go; the master’s analog ground plane
where sensitive analog components, the master’s
GND pin, and V
slave’s analog ground plane where the slave’s GND
DD
OUT
bypass capacitor) together near the controller IC.
, and D1 anode). If possible, make all these
CC
bypass capacitor go; and the
Layout Procedure
DD
bypass
CC
IN
,