MB3773PF-G-BND-JNE1 Fujitsu Semiconductor America Inc, MB3773PF-G-BND-JNE1 Datasheet - Page 6

• Manufacturer Part Number: MB3773PF-G-BND-JNE1
• Description: IC POWER SUPPLY MONITOR 8SOP
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of MB3773PF-G-BND-JNE1

• Applications: Power Supply Monitor
• Voltage - Supply: 3.5 V ~ 16 V
• Current - Supply: 600µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Other names: 865-1022

6
MB3773
OPERATION SEQUENCE
(1) When Vcc rises to about 0.8 V, RESET goes “Low” and RESET goes “High”.
(2) When Vcc rises to V
(3) When C
(5) C changes from the charge into the discharge when the voltage of C
(6) When the clock is cut off, gets, and the voltage of C
(7) Reset time in operating watch-dog timer:T
(8) When Vcc falls on V
(9) When Vcc goes up to V
(10) Reset of the output is released after T
(11) While power supply is off, when Vcc becomes V
(12) The reset output is maintained until Vcc becomes 0.8 V when Vcc falls on 0 V.
(4) C changes from the discharge into the charge if the clock (Negative edge) is input to the CK terminal
threshold ( : = 1.4 V) .
The pull-up current of approximately 1 A (Vcc = 0.8 V) is output from RESET.
At this time, the output is being reset.
After T
Reset hold time: T
After releasing reset, the discharge of C
T
“Low” and RESET goes “High”.
Discharge time of C
Because the charging time of C
of reset of the clock, T
threshold ( : = 1.4 V) for reset.
Reset of the output is released after C
after that if the clock is normally input, operation repeats (4) and (5) , when the clock is cut off, operation
repeats (6) and (7) .
while discharging C
(4) and (5) are repeated while a normal clock is input by the logic system.
When Vcc is momentarily low,
After falling V
more.
After the charge of C
After that, when Vcc becomes V
PR
T
T
is not influenced by the CK input.
WD
WR
PR
(ms) : = 100
(ms) : = 20
T
reset of the output is released.
begins charging, RESET goes “High” and RESET goes “Low”.
SL
or less Vcc, the time to going up is the standard value of the Vcc input pulse width in V
PR
T
T
C
SH
.
SL
C
(ms) : = 1000
until reset is output: T
T
T
WD
T
( : = 4.2 V) , reset is output. C
is discharged, the charge is started if it is T
( : = 4.3V) , the charge with C
( F)
( F)
SH
becomes maximum T
, the charge with C
T
is added at accurate time from stop of the clock and getting to the output
SL
or less, (8) to (10) is repeated.
C
T
PR
T
( F)
reaches an off threshold for reset, and C
T
, after Vcc becomes V
starts, and watch-dog timer operation starts.
WR
WD
is charging time where the voltage of C
T
is watch-dog timer monitoring time.
is started.
WD
SL
T
or less, reset is output.
T
T
T
is rapidly discharged of at the same time.
starts.
falls on threshold ( : = 0.4 V) of reset on, RESET goes
WR
by minimum T
SH
or more, and the watch-dog timer starts.
PI
or more.
T
reaches a constant
WD
.
T
starts the discharge,
T
goes up to off
SH
or