MAX17480GTL+ Maxim Integrated Products, MAX17480GTL+ Datasheet - Page 44

• Manufacturer Part Number: MAX17480GTL+
• Description: IC CTRLR SERIAL VID 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17480GTL+

• Applications: Processor
• Current - Supply: 5mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Output Voltage Range: - 10 V to + 10 V
• Input Voltage Range: 4 V to 26 V
• Input Current: 5 mA
• Power Dissipation: 1778 mW
• Operating Temperature Range: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AMD 2-/3-Output Mobile Serial
VID Controller
Figure 12. SVI Bus START, STOP, and Data Change Conditions
Figure 13. SVI Bus Acknowledge
The SVI bus is not busy when both data and clock lines
remain high. Data transfers can be initiated only when
the bus is not busy. Figure 13 shows the SVI bus
acknowledge.
Starting from an idle bus state (both SVC and SVD are
high), a high-to-low transition of the data (SVD) line while
the clock (SVC) is high determines a START condition.
All commands must be preceded by a START condition.
A low-to-high transition of the SDA line while the clock
(SVC) is high determines a STOP condition. All opera-
tions must be ended with a STOP condition.
After generating a START condition, the bus master
transmits the slave address consisting of a 7-bit device
code (110xxxx) for the MAX17480. Since the
MAX17480 is a write-only device, the eighth bit of the
44
DATA OUTPUT
DATA OUTPUT
BY MAX17480
BY MASTER
______________________________________________________________________________________
SVC FROM
SVD
SVC
MASTER
CONDITION
START
S
CONDITION
START
S
Start Data Transfer (S)
Stop Data Transfer (P)
CLK1
DATA VALID
DATA LINE
D7
1
STABLE
Slave Address
Bus Not Busy
ALLOWED
CHANGE
OF DATA
CLK2
D6
2
slave address is 0. The MAX17480 monitors the bus for
its corresponding slave address continuously. It gener-
ates an acknowledge bit if the slave address was true
and it is not in a programming mode.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the high period of the clock signal. The data
on the line must be changed during the low period of
the clock signal. There is one clock pulse per bit of data.
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse that is associated with this acknowledge bit. The
device that acknowledges has to pull down the SVD
line during the acknowledge clock pulse so that the
SVD line is stable low during the high period of the
acknowledge-related clock pulse. Of course, setup and
hold times must be taken into account. See Figure 13.
NOT ACKNOWLEDGE
ACKNOWLEDGE
CLK8
D0
8
ACKNOWLEDGE
CLOCK PULSE
CLK9
9
CONDITION
STOP
P
SVD Data Valid
Acknowledge