MAX17480GTL+ Maxim Integrated Products, MAX17480GTL+ Datasheet - Page 33

• Manufacturer Part Number: MAX17480GTL+
• Description: IC CTRLR SERIAL VID 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17480GTL+

• Applications: Processor
• Current - Supply: 5mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Output Voltage Range: - 10 V to + 10 V
• Input Voltage Range: 4 V to 26 V
• Input Current: 5 mA
• Power Dissipation: 1778 mW
• Operating Temperature Range: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When the core SMPSs are configured in combined
mode (GNDS1 or GNDS2 pulled to V
MAX17480 current-mode architecture automatically
forces the individual phases to remain current bal-
anced. SMPS1 is the main voltage-control loop, and
SMPS2 maintains the current balance between the
phases. This control scheme regulates the peak induc-
tor current of each phase, forcing them to remain prop-
erly balanced. Therefore, the average inductor current
variation depends mainly on the variation in the current-
sense element and inductance value.
The MAX17480 current-limit circuit employs a fast peak
inductor current-sensing algorithm. Once the current-
sense signal of the SMPS exceeds the peak current-limit
threshold, the PWM controller terminates the on-time.
See the Core Peak Inductor Current Limit (ILIM12) sec-
tion in the Core SMPS Design Procedure section.
Figure 8. Startup Sequence
(VDD_PLANE_STRAP)
GNDS1 OR GNDS2
SMPS V
SVC/SVD
RESET_L
PGD_IN
PWRGD
DC_IN
SHDN
V
DDIO
OUT
______________________________________________________________________________________
Combined-Mode Current Balance
1
Peak Current Limit
2
2-BIT BOOT VID
AMD 2-/3-Output Mobile Serial
DDIO
20µs
3
), the
4
SERIAL MODE
Power-on reset (POR) occurs when V
approximately 3V, resetting the fault latch and preparing
the controller for operation. The V
(UVLO) circuitry inhibits switching until V
4.25V (typ). The controller powers up the reference once
the system enables the controller V
SHDN is driven high. With the reference in regulation, the
controller ramps the SMPS and NB voltages to the boot
voltage set by the SVC and SVD inputs:
The soft-start circuitry does not use a variable current
limit, so full output current is available immediately.
PWRGD becomes high impedance approximately 20µs
after the SMPS outputs reach regulation. The boot VID
is stored the first time PWRGD goes high. The
MAX17480 is in pulse-skipping mode during soft-start.
Figure 8 shows the MAX17480 startup sequence.
10µs
5
Power-Up Sequence (POR, UVLO, PGD_IN)
6
HIGH-Z
BLANK
7
t
20µs
8
START
VID Controller
BUS IDLE
=
(
1
V
mV s
BOOT
CC
/µ
CC
undervoltage-lockout
)
above 4.25V and
CC
CC
rises above
rises above
33