MAX17480GTL+ Maxim Integrated Products, MAX17480GTL+ Datasheet - Page 41

• Manufacturer Part Number: MAX17480GTL+
• Description: IC CTRLR SERIAL VID 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17480GTL+

• Applications: Processor
• Current - Supply: 5mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Output Voltage Range: - 10 V to + 10 V
• Input Voltage Range: 4 V to 26 V
• Input Current: 5 mA
• Power Dissipation: 1778 mW
• Operating Temperature Range: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Most of the following MOSFET guidelines focus on the
challenge of obtaining high-load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention.
The high-side MOSFET (N
the resistive losses plus the switching losses at both
V
Ideally, the losses at V
losses at V
losses at V
at V
R
es at V
V
R
wide range, the minimum power dissipation occurs
where the resistive losses equal the switching losses.
Choose a low-side MOSFET that has the lowest possible
on-resistance (R
package (i.e., one or two 8-pin SOs, DPAK, or D2PAK),
and is reasonably priced. Make sure that the DL gate dri-
ver can supply sufficient current to support the gate
charge and the current injected into the parasitic gate-to-
drain capacitor caused by the high-side MOSFET turning
on; otherwise, cross-conduction problems might occur
(see the Core SMPS MOSFET Gate Drivers section).
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (N
case power dissipation due to resistance occurs at the
minimum input voltage:
where I
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the R
power dissipation often limits how small the MOSFET
can be. Again, the optimum occurs when the switching
losses equal the conduction (R
side switching losses do not usually become an issue
until the input is greater than approximately 15V.
Calculating the power dissipation in the high-side
MOSFET (N
must allow for difficult quantifying factors that influence
the turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold voltage,
source inductance, and PCB layout characteristics. The
following switching-loss calculation provides only a very
IN(MIN)
IN(MIN)
DS(ON)
DS(ON)
IN(MAX)
IN(MAX)
LOAD
PD (N Resistive) =
, consider reducing the size of N
but with higher C
and V
to lower C
IN(MIN)
, consider increasing the size of N
IN(MAX)
H
H
is the per-phase current.
) due to switching losses is difficult since it
are significantly higher than the losses at
IN(MAX)
DS(ON)
DS(ON)
are significantly higher than the losses
______________________________________________________________________________________
, with lower losses in between. If the
GATE
Core MOSFET Power Dissipation
IN(MIN)
Core Power-MOSFET Selection
. Calculate both of these sums.
required to stay within package
), comes in a moderate-sized
). If V
⎛
⎝ ⎜
GATE
H
V
OUT
V
) must be able to dissipate
IN
should be roughly equal to
). Conversely, if the loss-
IN
⎞
⎠ ⎟
DS(ON)
I
does not vary over a
LOAD
2
) losses. High-
R
DS O
H
H
), the worst-
AMD 2-/3-Output Mobile Serial
( N N )
H
(increasing
(reducing
rough estimate and is no substitute for breadboard
evaluation, preferably including verification using a
thermocouple mounted on N
:
where C
I
typ), and I
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the C
x V
MOSFET chosen for adequate R
voltages becomes extraordinarily hot when biased from
V
lower parasitic capacitance.
For the low-side MOSFET (N
dissipation always occurs at maximum input voltage:
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
I
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, the circuit can be “overde-
signed” to tolerate:
where I
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good-sized heatsink to handle the over-
load power dissipation.
Choose a Schottky diode (D
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. As a gen-
eral rule, select a diode with a DC current rating equal
to 1/3 the load current per phase. This diode is optional
and can be removed if efficiency is not critical.
The boost capacitors (C
enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1µF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current appli-
cations driving large, high-side MOSFETs require boost
capacitors larger than 0.1µF. For these applications,
I
GATE
LOAD(MAX)
LOAD MAX
PD (N Resistive) =
IN(MAX)
PD (N Switching) =
IN
(
2
is the peak gate-drive source/sink current (1A,
L
x f
RSS
PEAK(MAX)
H
)
, consider choosing another MOSFET with
=
SW
LOAD
I
PEAK MAX
, but are not quite high enough to exceed
is the reverse transfer capacitance of N
switching-loss equation. If the high-side
(
is the per-phase current.
)
−
⎡
⎢
⎢ ⎢
⎣
∆
1−
is the maximum valley current
VID Controller
I
INDUCTOR
(
⎛
⎜
⎜
⎝
V
V
2
IN MAX
BST
IN MAX
V
OUT
(
(
H
) must be selected large
L
:
L
=
) with a forward voltage
), the worst-case power
Core Boost Capacitors
I
)
)
PEAK MAX
)
⎞
⎟
⎟
⎠
2
DS(ON)
⎤
⎥
⎥
⎦
⎛
⎜
⎝
⎛
⎜
⎝
η
(
C
I
LOAD
TOTAL
I
RSS SW
GAT
) )
−
f
at low battery
⎛
⎜ ⎜
⎝
E E
I
LOAD MAX
⎞
⎟
⎠
2
⎞
⎟
⎠
R
I
(
LOAD
DS ON
2
(
)
LIR
41
)
H
⎞
⎟ ⎟
⎠
,