IR3529MTRPBF International Rectifier, IR3529MTRPBF Datasheet - Page 12

• Manufacturer Part Number: IR3529MTRPBF
• Description: IC CTRL XPHASE CPU/ASIC 20-MLPQ
• Manufacturer: International Rectifier
• Series: XPhase3™r

Specifications of IR3529MTRPBF

• Applications: Processor
• Current - Supply: 2mA
• Voltage - Supply: 8 V ~ 16 V
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: *
• Package: 20-Lead MLPQ
• Circuit: X-Phase Phase IC
• Iout (a): 4.0A Gate Driver
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: IR3529MTRPBFTR

share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its duty cycle and
output current. The current share amplifier is internally compensated so that the crossover frequency of the current
share loop is much slower than that of the voltage loop and the two loops do not interact. For proper current sharing
the output of current sense amplifier should not exceed (VCCL-1.4V) under all operating condition.
IR3529 THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3529 is shown in Figure 5, and specific features are discussed in the following
sections.
Tri-State Gate Drivers
The gate drivers are design to provide a 2A source and sink peak current (Bottom gate driver can sink 4A). An
adaptive non-overlap circuit monitors the voltage on the GATEH and GATEL pins to prevent MOSFET shoot-
through current and minimizing body diode conduction. The non-overlap latch is added to eliminate erroneous
triggering caused by the switching noise. A fault condition is communicated to the phase IC via the control IC’s
error amplifier without an additional dedicated signal line. The error amplifier’s output is driven low in response to
any fault condition detected by the controller, such as VCCL under voltage or output overload, disabling the phase
IC and activating Body Braking
drives the bottom gate output low. This tri-state operation prevents negative inductor current and negative output
voltage during power-down.
PHSIN
ISHARE
CLKIN
EAIN
VCC
DACIN
LGND
ILL
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VCCL
0.8V
.
.
100mV
200mV
.
Turbo
OVP
COMPARATOR
PSI_SY NC
VCC
-
+
+
-
.
BODY BRAKING
COMPARATOR
.
OC
TM
.
CALIBRATION
.
.
. The IR3529 Body Braking
PWM Comparator
OVP
Share Adjust
Amplifier
Latch
.
PHSIN
&
.
OC
PSI_SY NC#
PSI_SY NC
.
.
PWM_RESET
.
.
.
.
.
PSI_SY NC
Generation
Figure 5: Block diagram
.
SHIFT
Pulse
PGND
GATEL
SW
GATEH
.
CSREF
.
.
.
.
Non-Overlap
Time Generator
.
.
.
.
Negative Current
Comparator &
Latch
SHIFT
TM
+
.
.
D
CLK
+
comparator detects the low signal at the EAIN and
QB
Q
.
PSI_SY NC#
PSI_SY NC
CALIBRATION
CSAOUT
.
.
.
CURRENT SENSE
AMPLIFIER
X33
PHSIN
-
+
.
.
DEBUG
COMPARATOR
.
.
.
.
.
.
.
.
.
.
.
GATEH
Enable
GATEL
Enable
+
-
OC
.
.
.
PSI# Comparator
8 Count Delay
0.15V
Cycle-by-
Cycle OCP
Synchronous
Rectification
Disable
.
.
VCCL
D
CLK
&
February 12, 2010
Q
GATE H
Driver
.
.
VCCL
GATE L
Driver
.
.
.
SHIFT
0.75 DACIN
200uA
IR3529
BOOST
PHSOUT
VCCL
GATEH
OCSET
SHIFT
SW
GATEL
PGND
CSIN-
CSIN+
PSI#