MC10XS3435BPNA Freescale Semiconductor, MC10XS3435BPNA Datasheet - Page 35

• Manufacturer Part Number: MC10XS3435BPNA
• Description: IC SWITCH HIGH SIDE QUAD 24-QFN
• Manufacturer: Freescale Semiconductor
• Type: High Side Switchr

Specifications of MC10XS3435BPNA

• Number Of Outputs: 4
• Rds (on): 2 x 10 mOhm, 2 x 35 mOhm
• Internal Switch(s): Yes
• Current Limit: 5A
• Voltage - Input: 6 ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EMC PERFORMANCES
board in accordance with the typical application schematic.
SERIAL INPUT COMMUNICATION
messages. A message is transmitted by the MCU starting
with the MSB D15 and ending with the LSB, D0
Each incoming command message on the SI pin can be
interpreted using the following bit assignments: the MSB,
D15, is the watchdog bit (WDIN). In some cases, output
selection is done with bits D14 : D13. The next three bits,
D12: D10, are used to select the command register. The
DEVICE REGISTER ADDRESSING
addresses (D[14:10]) and their impact on device operation.
Table 10. SI Message Bit Assignment
Table 11. Serial Input Address and Configuration Bit Map
R)
Analog Integrated Circuit Device Data
Freescale Semiconductor
V
SI Register
CONFR0_s WDIN
CONFR1_s WDIN
V
state after
RST=0 or
x = Don’t care.
s = Output selection with the bits A
STATR_s
PWMR_s
Register
DD(FAIL)
SUPPLY(PO
condition
OCR_s
CALR
All following tests are performed on Freescale evaluation
SPI communication is accomplished using 16-bit
The following section describes the possible register
GCR
Bit Sig
MSB
LSB
or
WDIN
WDIN
WDIN
WDIN
WDIN
D15
0
D14 D13 D12 D11 D10 D9
A
A
A
A
X
0
0
0
1
1
1
1
A
A
A
A
X
0
0
0
0
0
0
0
SI Msg Bit
X
0
0
0
0
1
1
1
D14
D12
D8:D0
D15
D9
X
0
0
1
1
0
0
1
:
:
D13
D10
0
1
0
1
0
1
1
X
1
A
0
0
0
0
0
0
0
0
0
as defined in
VDD_FAI
Xenon_s
28W_s
L_en
D8
0
0
0
1
0
LOGIC COMMANDS AND REGISTERS
Watchdog in: toggled to satisfy watchdog requirements.
Register address bits used in some cases for output selection (
Register address bits.
Not used (set to logic [0]).
Used to configure the inputs, outputs, and the device protection features and SO status content.
PWM_en
BC1_s
ON_s
Table
D7
(Table
0
0
0
0
0
12.
CLOCK_sel
unlimited_s
PWM6_s
10).
BC0_s
Retry_
D6
0
0
1
0
Retry_dis_s
DIR_dis_s
SI Data
TEMP_en
PWM5_s
OC1_s
transients on the VPWR line (per ISO 7637-2).
CISPR25 emission standard and 200 V/m or BCI 200 mA
injection level for immunity tests.
remaining nine bits, D8 : D0, are used to configure and control
the outputs and their protection features.
accommodate those applications where daisy-chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of 16 bits. Any attempt made to
latch in a message that is not 16 bits will be ignored.
configure the device and to control the state of the outputs.
Table 11
D5
0
0
0
The device is protected in case of positive and negative
The 10XS3435 successfully meets the Class 5 of the
Multiple messages can be transmitted in succession to
The 10XS3435 has defined registers, which are used to
Message Bit Description
CSNS_en
OS_dis_s
PWM4_s
OC0_s
summarizes the SI registers.
SR1_s
SOA4
D4
1
0
OLON_dis_s
PWM3_s
OCHI_s
CSNS1
SR0_s
SOA3
D3
1
0
LOGIC COMMANDS AND REGISTERS
FUNCTIONAL DEVICE OPERATION
OLOFF_dis_s OLLED_en_s CSNS_ratio_s
DELAY2_s
OLCO1_s
PWM2_s
CSNS0
Table 12
SOA2
D2
0
0
).
DELAY1_s
OLCO0_s
PWM1_s
SOA1
D1
X
1
0
OC_mode_s
DELAY0_s
PWM0_s
10XS3435
OV_dis
SOA0
D0
1
0
35