MC10XS3435BPNA Freescale Semiconductor, MC10XS3435BPNA Datasheet - Page 20

• Manufacturer Part Number: MC10XS3435BPNA
• Description: IC SWITCH HIGH SIDE QUAD 24-QFN
• Manufacturer: Freescale Semiconductor
• Type: High Side Switchr

Specifications of MC10XS3435BPNA

• Number Of Outputs: 4
• Rds (on): 2 x 10 mOhm, 2 x 35 mOhm
• Internal Switch(s): Yes
• Current Limit: 5A
• Voltage - Input: 6 ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5. Dynamic Electrical Characteristics (continued)
otherwise noted. Typical values noted reflect the approximate parameter means at T
otherwise noted.
20
SPI INTERFACE CHARACTERISTICS
Notes
10XS3435
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Maximum Frequency of SPI Operation
Required Low State Duration for RST
Rising Edge of CS to Falling Edge of CS (Required Setup Time)
Rising Edge of RST to Falling Edge of CS (Required Setup Time)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Required High State Duration of SCLK (Required Setup Time)
Required Low State Duration of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
SI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to SI (Required Setup Time)
SO Rise Time
SO Fall Time
SI, CS, SCLK, Incoming Signal Rise Time
SI, CS, SCLK, Incoming Signal Fall Time
Time from Falling Edge of CS to SO Low-impedance
Time from Rising Edge of CS to SO High-impedance
39.
40.
41.
42.
43.
44.
Characteristics noted under conditions 6.0 V ≤ V
C
C
L
L
= 80 pF
= 80 pF
Parameters guaranteed by design.
RST
Maximum setup time required for the 10XS3435 is the minimum guaranteed time needed from the microcontroller.
Rise and Fall time of incoming SI,
Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on
Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on
low duration measured with outputs enabled and going to OFF or disabled condition.
Characteristic
(40)
(39)
CS
(42)
(42)
, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
(42)
(42)
(43)
(44)
PWR
≤ 20 V, 3.0 V ≤ V
(41)
(41)
(41)
(41)
(41)
(41)
DD
t
Symbol
t
t
t
SI (HOLD)
t
WSCLKh
t
t
WSCLKl
SO(DIS)
t
t
SO(EN)
SI (SU)
t
WRST
t
t
f
ENBL
LEAD
t
t
t
RSO
FSO
LAG
≤ 5.5 V, - 40°C ≤ T
RSI
SPI
FSI
CS
CS
.
CS
A
= 25°C under nominal conditions unless
Min
.
10
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Analog Integrated Circuit Device Data
A
≤ 125°C, GND = 0 V unless
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Freescale Semiconductor
Max
500
8.0
1.0
5.0
50
50
60
37
49
13
13
13
13
60
60
–
Unit
MHz
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns